0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

Abstract

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

1. Introduction

Bulk-driven (BD) techniques have gained significant attention among circuit designers in recent years [1,2,3,4,5] because they eliminate the threshold voltage limitation when driving MOS field-effect transistor (MOSFET) devices via their bulk (body) terminals. The effectiveness of the BD approach has been particularly evident in implementing Operational Transconductance Amplifiers (OTAs) that function with supply voltages from 400 mV down to 250 mV [6,7,8,9,10,11,12,13,14,15,16,17,18,19]. This approach allows for the widest common-mode input range, nearly providing rail-to-rail limits. Furthermore, it often results in quiescent current consumption of only a few microamperes or less, which is achieved by properly biasing MOSFETs in their sub-threshold region. The above properties meet the rising demand for ultra-low-voltage, ultra-low-power integrated circuits (ICs) in portable, wearable, and implantable electronics [20,21,22,23] but also in the Internet of Things and in the automotive field, which require the development of new circuit topologies and design methodologies aimed at preserving the performance characteristics of established CMOS solutions while enhancing input/output voltage swing and reducing the necessary supply voltage, particularly in the analog domain.

In this framework, the second-generation Current Conveyor, CCII, is a versatile three-terminal (namely, Y, X, and Z terminals) block that provides distinctive performance as it brings together voltage-mode processing characteristics (the voltage follower action between the Y and X terminals) with current-mode ones (the current follower action between X and Z terminals). CCIIs have indeed been used for active filter implementation and are found to be building blocks of transimpedance and current feedback operational amplifiers, voltage, and current operational amplifiers [24,25,26,27].

A comprehensive review of the recent literature reveals that numerous publications explore novel CCII implementations with low-voltage and low-power capabilities that also exploit body-driven and subthreshold techniques to attain rail-to-rail performance [28,29,30,31,32,33]. In this paper, we present an alternative high-accuracy body-driven CCII solution supplied from 0.35 V and with a 2.86 µA total quiescent current (758 nA in the two output branches). Among the most relevant performances, thanks to the high open-loop gain and exploitation of cascoded current mirror topologies, the circuit provides accurate voltage (Y to X) and current (X to Z) transfers with a −3 dB frequency of 1.33 MHz and 2.13 MHz, respectively, and with an efficient current drive capability of around 2.5 µA.

Compared to other sub-1V solutions, the proposed design achieves superior current drive efficiency. This metric, defined as the ratio of maximum output current to total quiescent current, is particularly important in targeted battery-operated or even battery-less applications.

The rest of the paper is organized as follows. The presented solution is described in Section 2, where particular focus is directed towards elucidating the primary novel design solutions and fundamental design equations. Section 3 delves into the simulations conducted to assess the proposed solution, while in Section 4 the paper concludes with the authors presenting their findings and drawing conclusions.

2. The Proposed Solution

The proposed solution is depicted in Figure 1 and was derived from the OTA configuration presented by one of the authors in a recently published work that employs MOSFETs in the subthreshold region and strategically leverages the body terminals to enhance small-signal and large-signal performance [19].

Our proposed current-conveyor circuit introduces several key modifications compared to the design presented in [19]. Firstly, we introduce a current branch replicating current at terminal X in terminal Z. Secondly, we remove the Slew-Rate Enhancer section of [19] to eliminate nonlinearities inherent to this highly nonlinear circuit. Finally, we employ extensive transistor cascoding to achieve superior DC and AC matching, while also optimizing loop gain and the equivalent resistance at terminal Z. Moreover, while reference [19] focuses on off-chip, high-drive applications, our CCII is specifically designed for on-chip, low-load capacitance applications. This necessitates a distinct design approach to optimize for these contrasting use cases.

The solution is based on local positive feedback for improved input transconductance which is achieved through the bodies of $M_3$–$M_4$, and dynamic threshold voltage control to boost the current drive capability is implemented with the bodies of $M_{13}$–$M_{14}$. It is to be noted that a trade-off among simplicity, current transfer accuracy, linearity, high impedance, and voltage compliance is achieved through supply-biased cascode structures. In other words, all the n-channel (p-channel) cascode transistors have their gates connected to $V_{DD}$ ($V_{SS}$).

Specifically, the solution is made up of four sections: the BD rail-to-rail input stage ($M_1$–$M_4$, $R_1$–$R_2$), the second gain stage with a differential-to-single-ended function ($M_5$–$M_{12}$) the third noninverting gain stage ($M_{13}$–$M_{20}$), and a replica of the output branch ($M_{21}$–$M_{24}$) which, working in class AB, mirrors the current from terminal X into terminal Z.

The input stage utilizes transistors $M_1$ and $M_2$, forming a minimum-supply tail-less body-driven pair without a dedicated current source transistor. A constant current ($I_B$) establishes the quiescent current through this pair via the diode-connected transistor $M_R$ (with the body connected to terminal Y). The actual current flowing through M1 and M2 is determined by the mirror ratio (W/L)_1,2/(W/L)_R, where W and L represent the width and length of the transistors. Due to the virtual short at the input of the OTA ($V_X$ = $V_Y$), these transistors share the same body voltage at DC, resulting in the same threshold voltage.

The active load for the input stage comprises transistors $M_3$ and $M_4$, with negative feedback resistors $R_1$ and $R_2$ playing a crucial role in amplifying differential signals. This load configuration allows the inherently pseudo-differential pair ($M_1$ and $M_2$) to effectively handle differential inputs. Local positive feedback is implemented by connecting the body of $M_3$ to the drain of $M_4$ and vice versa, enhancing the overall transconductance of the input stage.

The second stage, designed for high output impedance and for converting differential to single-ended output, consists of transistors $M_5$–$M_{12}$. The quiescent current in this stage mirrors the current in the first stage through $M_9$ and $M_{10}$ because $M_3$ and $M_4$ act as diode-connected devices at DC, ensuring no current flows through $R_1$ and $R_2$ at DC.

Given that $V_{BS3,4}$ = $V_{GS3,4}$ while $V_{BS9,10}$ = 0, the current mirror gain is reduced compared to a conventional current mirror, where this factor equals 1 [19].

The third gain stage, consisting of common-source transistor $M_{17}$ with cascode $M_{19}$ and active loads $M_{13}$–$M_{16}$ and $M_{18}$, $M_{20}$, regulates the X branch’s quiescent current through the current mirror gains of $M_{3,4}$ to $M_{17}$, and of $M_{13}$ to $M_{14}$. Notably, the pull-down $i_X$ current from $M_{18}$ can exceed the quiescent value, like the pull-up $i_X$ current from $M_{14}$, although to a lesser extent. In fact, both $M_{14}$ and $M_{18}$ operate in class AB but the positive-going output step responds slower than the negative-going step due to the limited variation of the gate voltage of $M_{17}$ compared to the gate voltage of $M_{18}$. To address this asymmetry, the gain in the current mirror formed by transistors $M_{13}$–$M_{14}$ is dynamically adjusted based on the required current level. This is achieved by connecting the body of $M_{13}$ to the drain of $M_4$ and the body of $M_{14}$ to the drain of $M_8$ ($M_{12}$), as shown in Figure 1. This configuration leverages the dependence of the threshold voltage of $M_{13}$ and $M_{14}$ on variations in $V_{X2}$ and $V_{X3}$, boosting the current mirror gain when the output stage supplies current, as explained in [19].

The output of this stage is tied to the inverting input of the input pair $M_1$–$M_2$ providing unity gain configuration through high-gain negative feedback and hence ensuring virtual short between voltages at nodes Y and X.

The current flowing in terminal X through $M_{14}$ and $M_{18}$ is mirrored to terminal Z thanks to the class-AB current mirror made up of transistors $M_{21}$–$M_{24}$ replicating the branch formed by $M_{14}$, $M_{16}$, $M_{18}$, and $M_{20}$.

Capacitor $C_c$ provides frequency compensation. Transistor dimensions and other design parameters are summarized in

Table 1. Transistor dimensions of circuit in Figure 1.

Device	W/L (µm/µm)
MR, M1, M2	34/0.5
M3, M4	8/1
M5, M6	160/1
M7, M8	9/0.5
M11, M12	2/0.5
M9, M10	32/1
M13	50/0.5
M15	5/0.5
M17	16/1
M18	1.5/0.5
M14, M21	200/0.5
M16, M22	20/0.5
M18, M23	60/2
M20, M24	6/1

and

Table 2. Other design parameters of circuit in Figure 1.

Param	Value
VDD–VSS	0.35 V
IB	200 nA
R1, R2	250 kΩ
CC	200 fF
CL	1 pF

.

Small-Signal Analysis and Noise

Owing to the negative feedback, the CCII voltage transfer from terminal Y to X is as follows:

$$\frac{V_X}{V_Y}=\frac{1}{1+\frac{1}{T\left(s\right)}}\approx \frac{1}{1+\frac{1}{T\left(0\right)}} \frac{1}{1+\frac{s}{{\omega }_{GBW}}}$$

(1)

where T(0) is the loop gain $G_{mEQ}{r}_{oX3}{g}_{m17}{r}_{oX}$, in which $r_{oX3}$ and $r_{oX}$ are equivalent resistances at the drain of $M_8$, $M_{12}$ and $M_{16}$, $M_{20}$, respectively, and $G_{mEQ}$ is given by $g_{mb1,2}/(1-g_{mb3,4}{r}_{X1,2}$), due to the local positive feedback operated by the bodies of $M_3$ and $M_4$, and as detailed in [19]. As usual, ${\omega }_{GBW}$ is given by $G_{mEQ}/C_c$.

It is seen that the DC value of (1) tends to be 1 for high values of T(0).

The equivalent (closed loop) small signal resistance at terminal X is approximately given by the following equation:

$$r_X \approx \frac{r_{oX}}{T\left(0\right)}=\frac{g_{m20}{r}_{o18}{r}_{o20} // g_{m16}{r}_{o14}{r}_{016}}{T\left(0\right)}$$

(2)

and the small signal equivalent resistance at terminal Z is simply as follows:

$$r_Z=g_{m24}{r}_{o23}{r}_{024} // g_{m22}{r}_{o21}{r}_{022}$$

(3)

The CCII noise performance can be modeled by considering the equivalent input noise voltage of the voltage buffer (v_nY, in series to terminal Y) and the equivalent input noise current of the current buffer (i_nX, in parallel to terminal X), as shown in Figure 2 [34].

The equivalent input-referred noise voltage spectral density of the CCII, $\overline{v_{nY}^2}$, accounts for the contribution of transistors $M_1$ and $M_2$, that of transistors $M_3$ and $M_4$, and of resistors $R_{1,2}$. It can be approximated as in Equation (4), considering only white noise for simplicity [9].

$$\begin{gathered} \overline{v_{nY}^2}\approx 2\overline{v_{n1,2}^2}{\left(\frac{g_{m1,2}}{g_{mb1,2}}\right)}^2+2\overline{v_{n3,4}^2}{\left(\frac{g_{m3,4}}{g_{mb1,2}}\right)}^2+\overline{v_{nR1,2_Y}^2} \\ =2\frac{2}{3}4kT\frac{1}{g_{mb1,2}}\left(\frac{g_{m1,2}}{g_{mb1,2}}+\frac{g_{m3,4}}{g_{mb1,2}}\right)\Delta f \\ +4kT{R}_{1,2}{\left(\frac{1}{g_{mb1,2r_{o1}}}\right)}^2\left[1+{\left(1+\frac{2r_{o1}}{R_{1,2}}\right)}^2\right]\Delta f \end{gathered}$$

(4)

where $\overline{v_{ni}^2}$ is the gate-referred noise voltage spectral density of the i-th transistor, $\overline{v_{nR1,2Y}^2}$ is the input-referred noise contribution of the resistors R₁ and R₂, r_o1 is the output resistance of M_1, and k and T are the Boltzmann’s constant and the absolute temperature.

In the above expression, noise from M_R is neglected since it is seen as a common-mode signal and is rejected. Additionally, the noise from the R_1,2 results is considered to be negligible by the following equation:

$$\left(g_{m1,2}+g_{m3,4}\right)r_{o1}\gg \frac{3}{4}\frac{R}{r_{o1}}\left[1+{\left(1+\frac{2r_{o1}}{R}\right)}^2\right]$$

(5)

Unfortunately, (5) is not fulfilled in our design.

The noise current generator, i_nX, is equal to the output noise at terminal Z when terminal X is floating. The mean-square value can easily be calculated as follows:

$$\overline{i_{nX}^2}\approx g_{m14}^2\overline{v_{n14}^2}+g_{m21}^2\overline{v_{n21}^2}+g_{m18}^2\overline{v_{n18}^2}+g_{m23}^2\overline{v_{n23}^2}$$

(6)

3. Simulation Results

The circuit was designed and simulated using a standard 65 nm CMOS technology supplied by TSMC and accessed through EUROPRACTICE. The supply voltage is 350 mV and the total current consumption is 2.86 μA, with the current in the X and Z output branches equal to 758 nA each.

Figure 3a,b shows the Bode plots, magnitude, and phase, of the open loop gain from the body of $M_2$ and the drain of $M_{16}$ and $M_{20}$, with a load capacitance of 1 pF. The DC gain is around 70 dB and the unity gain bandwidth is 600 kHz, with more than 70° phase margin.

The Bode plots of the (closed-loop) voltage transfer (from Y to X) are shown in Figure 4a,b. The low-frequency gain is −4.096 mdB. Montecarlo simulations on 1000 iterations show 68 mdB of standard deviation. The −3 dB frequency is 1.33 MHz.

Additional simulations indicate little changes in the low-frequency gain with different DC levels of the voltage at the Y terminal in the range [20 mV–350 mV]. The same marginal variations are found for different operating temperatures in the range [−40 °C–120 °C].

The Bode plots of the current transfer (from X to Z) are shown in Figure 5a,b. The low-frequency gain is −2.087 mdB. Montecarlo simulations on 1000 iterations show 72.5 mdB of standard deviation. The −3 dB frequency is 2.13 MHz. A 14.1 dB peak is observed at 1.38 MHz.

The magnitude of the impedance at terminal Y versus the frequency is shown in Figure 6. It decreases with the frequency while maintaining a substantial high value. For example, it is 118 GΩ at 10 Hz, 150 MΩ at 10 kHz, and 1.6 MΩ at 1 MHz. The parasitic capacitance at this terminal is evaluated to be 96.5 fF.

Figure 7 shows the input current at terminal Y as a function of $V_Y$. Under a 175 mV $V_Y$, the input current is 378.9 fA (with 189 fA flowing into each bulk of $M_R$ and $M_1$). The maximum input current, for $V_Y$ equal to 0, is 26 pA.

The magnitude of the impedance at terminal X versus frequency is shown in Figure 8. The low-frequency impedance is 1.8 kΩ. The inductive behavior is apparent because of the peaking of around 520 kΩ at around 1.5 MHz. The magnitude of the impedance at terminal Z versus frequency is shown in Figure 9, and the low-frequency value is 7.46 MΩ.

The DC transfer characteristic of the voltage transfer $V_X$ versus $V_Y$ and of the current transfer $I_Z$ versus $I_X$ are illustrated in Figure 10 and Figure 11, respectively. The rail-to-rail input (Y) and output (X) voltage ranges are apparent from Figure 10. Figure 11 shows that the linear current range is around ±2.5 µA (the quiescent current in the two branches with nodes X and Z is around 758 nA each). The systematic offset current at terminal Z is 1.1 pA.

The Total Harmonic Distortion (THD) of the voltage at terminal X for different input sinusoidal amplitudes and frequencies is shown in Figure 12. It shows that the THD at 1 kHz and 10 kHz equals 1% at about 340${\mathrm{mV}}_{p-p}$ and 305${\mathrm{mV}}_{p-p}$ input, respectively. The THD of the current at terminal Z (tied to a voltage equal to $V_{DD}/2$) for different input sinusoidal amplitudes and frequencies is shown in Figure 13. It shows that the THD at 1 kHz and 10 kHz equals 1% at about 2.8 µA and 2.7 µA input, respectively.

As discussed in the previous section, two equivalent noise sources are necessary to characterize a CCII. The equivalent noise voltage generator (at terminal Y) and the equivalent noise current generator (at terminal X) spectral densities are plotted in Figure 14a and Figure 14b, respectively. White noise levels are, respectively, 849 $\frac{nV}{\sqrt{Hz}}$ and 943 $\frac{fA}{\sqrt{Hz}}$. In agreement with (5) and (7), the noise voltage main contributions are due to R_1,2 (44%), M_1,2 (27%), and M_3,4 (16%). The noise current main contributions are due to M₁₄, M₂₁, M₁₈, and M₂₃, giving more than 50% of the total.

Table 3. Performance comparison of low voltage CCIIs.

Ref.	[33] *	[28]	[29]	[30]	[31]	[32]		Proposed
Year	2003	2011	2012	2012	2017	2019		2024
Tech. (nm)	350	180	180	180	90	180		65
VDD (V)	1.5	0.8	1	0.5	0.4	0.3	0.5	0.35
IQ (μA)	173	80	10	60	4.5	63.3 × 10−3	1.01	2.86
DC Power (μW)	2595	64	10	30	1.8	0.019	0.509	1
Y-Input voltage range (%VDD)	73	95	100	80	n.a.	100	100	97
X-Input current range (μA)	±900	±7	±3	±15	n.a.	±0.024	±0.4	2.5
IXmax,Zmax/IQ	5.2	8.75 × 10−2	0.3	0.25	n.a.	0.379	0.396	0.87
RY (MΩ)	∞	∞	∞	∞	n.a.	703	664	150 @10 kHz
RX (Ω)	150	27	42	260	106	56 × 103	3 × 103	1.8 × 103
RZ (MΩ)	0.3	0.89	53	0.113	n.a.	94.7	8	7.46
Voltage gain VX/VY (mdB)	−20	0	0	−17.4	34.7	−11.3	−8.69*	−4.1
Current gain IZ/IX (dB)	−40	0	0	−34.8	0	−8.69	−8.69	−2.1
−3 dB BW VX/VY (MHz)	2.4 @CL = 10 pF	14	4.8	11	1	4.1 × 10−3 *	56.4 × 10−3 * @CL = 30 pF	1.33 @CL = 1 pF
−3 dB BW IZ/IX (MHz)	1.2	13	8.2	10	1.25	39.2 × 10−3	578 × 10−3	2.13

* Measured results.

summarizes the performance of the proposed CCII (last column) compared to recent low-voltage, low-power CCII implementations [28,29,30,31,32,33]. Notably, reference [33] is the only fully fabricated and measured design in the table. While both designs utilize a class AB configuration, reference [33] operates at a supply voltage exceeding 1 V. It can be observed that the trend favors reduced supply voltage and lower DC power consumption. However, maintaining acceptable values of equivalent resistance $R_X$, −3 dB frequencies for voltage and current transfer, and input current range at node X (which corresponds to the current drive capability at node Z) necessitates a trade-off between these parameters and current consumption. The proposed solution demonstrates good current utilization efficiency which can be defined as the ratio between the maximum input/output linear current ($I_{Xmax,Zmax}$) and the total quiescent current ($I_Q$). This efficiency metric highlights the proposed CCII’s ability to achieve high performance while maintaining low power consumption. Moreover, the −3 dB frequency of the voltage transfer is also good in comparison to the low I_Q utilized.

As a final remark in the conclusion of this section, being the solution based on the topology in [19] that was experimentally characterized and found in reasonable agreement with the simulations, we are confident that also the simulations of this CCII, implemented in the same CMOS technology, provide meaningful and quite accurate results, even under MOSFETs’ subthreshold regime.

4. Conclusions

This work demonstrated a 0.35 V high-performance CCII achieving rail-to-rail voltage operation at the Y terminal and class AB current operation at the Z terminal. The design leverages a previously developed low-voltage subthreshold bulk-driven CMOS OTA which strategically utilizes body terminals for enhanced small-signal and large-signal performance. The resulting circuit boasts high open-loop gain and cascoded current mirror topologies, leading to accurate voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. Under a total quiescent current consumption of 2.86 μA, the CCII provides a linear current drive of up to 2.5 µA, with one of the best figures of merit concerning current utilization.

This work contributes to the growing body of research on CCII implementations suitable for portable and implantable electronics and for emerging applications requiring high performance and sub-1V, low-power consumption.