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Volume 10
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Article

High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs

by
Hui Xu
1,
Le Zhou
1,
Huaguo Liang
2,*,
Zhengfeng Huang
2,
Cong Sun
1 and
Yafei Ning
1
1
College of Computer Science and Engineering, Anhui University of Science and Technology, Huainan 232001, China
2
School of Microelectronics, Hefei University of Technology, Hefei 230009, China
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(20), 2515; https://doi.org/10.3390/electronics10202515
Submission received: 22 September 2021 / Revised: 14 October 2021 / Accepted: 14 October 2021 / Published: 15 October 2021
(This article belongs to the Section Circuit and Signal Processing)
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Abstract

To avoid soft errors in integrated circuits, this paper presents two high-performance latch designs, namely LOCDNUTRL and LOCTNUTRL, protecting against double-node upset (DNU) and triple-node upset (TNU) in the harsh radiation environment. First, the LOCDNUTRL latch consists of two single-node upset (SNU) self-recovery modules and uses a C-element at the output. Next, based on the LOCDNUTRL latch, the LOCTNUTRL latch is proposed, which uses five extra inverters to fully tolerate TNU. Unlike the LOCDNUTRL latch, which uses an output level C-element as a voter, LOCTNUTRL is insensitive to the high-impedance state (HIS), making it more reliable for aerospace applications. The HSPICE simulation results, using a predictive technology model, show that the LOCTNUTRL latch saves 57.74% delay, 7.7% power consumption, 11.74% area cost, and 63.59% power delay production (PDP) on average compared with the state-of-the-art hardened latches. The process, voltage, and temperature variation analysis show that the proposed two latches are less sensitive to changes.
Keywords: soft errors; triple-node upsets; self-recoverable; c-element; clock gating; fast path soft errors; triple-node upsets; self-recoverable; c-element; clock gating; fast path

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MDPI and ACS Style

Xu, H.; Zhou, L.; Liang, H.; Huang, Z.; Sun, C.; Ning, Y. High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs. Electronics 2021, 10, 2515. https://doi.org/10.3390/electronics10202515

AMA Style

Xu H, Zhou L, Liang H, Huang Z, Sun C, Ning Y. High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs. Electronics. 2021; 10(20):2515. https://doi.org/10.3390/electronics10202515

Chicago/Turabian Style

Xu, Hui, Le Zhou, Huaguo Liang, Zhengfeng Huang, Cong Sun, and Yafei Ning. 2021. "High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs" Electronics 10, no. 20: 2515. https://doi.org/10.3390/electronics10202515

APA Style

Xu, H., Zhou, L., Liang, H., Huang, Z., Sun, C., & Ning, Y. (2021). High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs. Electronics, 10(20), 2515. https://doi.org/10.3390/electronics10202515

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