Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

Abstract

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage devices. D-flip-flops (DFFs) based on the traditional CMOS process have some shortcomings, including a large area, high power, and charge leakage when scaling down. However, memristors offer a new approach to the design of DFFs with improved performance. Two simplified edge-triggered DFFs are proposed to reduce the number of devices via the Memristor-Rationed Logic (MRL) method, which utilizes the characteristic of transmitting signals in the two-stage inversion structure. In addition, two new 4-bit Linear Feedback Shift Registers (LFSRs) are designed and verified using the proposed DFFs. Compared to the partially existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease the power consumption by 32.7% and 33.3% and shorten the delay time by 34.5% and 30.7% for the NOR and NAND gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major blocks of the Built-In Self-Test(BIST) circuit, and the simulation results confirm their correctness and feasibility.

1. Introduction

In 1971, Professor Chua predicted the existence of the fourth passive component besides resistance, capacitance and inductance, namely the memristor, which has a unique hysteresis curve in the I–V plane [1]. However, the memristor remained a theoretical concept for many years, until the HP Lab team implemented the first physical memristor using titanium dioxide in 2008 [2]. This proved the feasibility of the memristor and was marked as a significant milestone. Since then, the memristor has received considerable attention from researchers and scientists.

Despite improvements in CMOS technology, the scaling down of devices has become increasingly challenging due to leakage, power increases and circuit reliability reductions, etc. Consequently, energy-efficient and high-speed switching is no longer the main focus. However, the rise of memristors offers a promising approach to improving the performance of computer systems because of their advantages, such as their small size, high density, low power consumption, fast switching speed and even in-memory computing, which can break through the bottleneck of the Von Neumann architecture. In recent years, memristors have been applied in various fields, including chaotic circuits [3,4,5], digital circuits [6,7,8,9,10,11,12] and neural networks [13,14,15]. Several logic operations based on memristors have been proposed so far, such as Memristor-Aided Logic (MAGIC) [16], Material Implication (IMPLY) [17] and Memristor-Ratioed Logic (MRL) [18]. However, the fan-out number of cascade MAGIC is limited by its weak driving ability, because series resistors have a partial voltage determined the memristors’ resistance. Additionally, the logic operation can be destructive for above-threshold voltages. IMPLY needs additional operational steps and has similar limitations. Hence, it is necessary to use active devices such as transistors to power passive components such as memristors and circuits. Herein, hybrid CMOS–memristor logic gates are employed to design subsequent sequential circuits.

Significant efforts have been made to enhance the performance of flip-flops, to obviate the shortcomings of the traditional CMOS technology in terms of chip area and power dissipation. An area-efficient flip-flop triggered by a dual-edge implicit pulse has been successfully developed by researchers using MOSFETs, reducing the power consumption by improving clock gating using a modified particle swarm optimization (MPSO) algorithm and decreasing the delay time via tristate inverters [19]. A flip-flop with an improved display pulse was proposed in ref. [20] to reduce the number of transistors while optimizing the speed and power dissipation compared to the existing display-pulse ones. In 2020, a thin-film complementary flip-flop circuit based on full-oxide thin-film transistors (n-type indium gallium zinc oxide and p-type tin monoxide) was proposed for the first time [21]. To further reduce the chip area, nanotechnology was applied, and a carbon nanotube field-effect transistor (CNFET) was also introduced to replace the traditional CMOS transistors in the design of a dynamic double-edge-triggered DFF, which reduced the power dissipation and delay time [22].

Although parameters such as the power and area of devices are improved as they are scaled down, the traditional CMOS process is unable to maintain Moore’s law. The MRL method is not only compatible with CMOS, but also has area and energy efficiency. Therefore, a linear feedback shift register was reported in ref. [23] using the hybrid CMOS–memristor, which has the characteristics of low power consumption and a fast conversion speed. However, there are more transistors applied in the design of this register.

As integrated circuit (IC) manufacturing process technologies have advanced to the deep sub-micron or even nanometer scale, the complexity and integration of circuit architectures is increasing more significantly. Consequently, the testing of ICs has already become a critical factor in terms of reducing the possibility of product failures and ensuring market competitiveness without full testability. Although automatic test equipment (ATE) can be used to test and analyze ICs, it is a time-consuming and costly process. To deal with this, an automatic on-chip testing methodology with a built-in self-test (BIST) was proposed in ref. [24]. Additionally, a hybrid logic built-in self-test (LBIST) was reported in ref. [25], which has the advantages of reducing the test time and quickly locating faults in the circuit during detection.

Therefore, NOR and NAND gate circuits are designed using the MRL structure, which has been optimized by adopting transistors implemented with a 50 nm BSIM4 model [26]. Based on these two logic gates, two types of DFFs with different trigger modes and structures are proposed. In comparison, there are fewer devices employed in the edge-triggered structure to maintain blocking. Then, new linear feedback shift registers are designed with these DFFS and used in a built-in self-test (BIST) and other aspects. The circuit architecture of the traditional CMOS processes not only occupies a large amount of chip area but also increases the costs. Therefore, nanoscale memristor devices are introduced into the BIST circuit design herein, in order to reduce the area and power consumption and improve the speed, etc., efficiently.

2. Memristor-Based Logic Gates

2.1. Memristor Model

HP Labs fabricated the first physical memristor device using titanium dioxide [2], as shown in Figure 1, where D is the total length, and $W_1$ and $W_2$ are the widths of the doped region and the undoped region, respectively. When a forward bias is applied to the device, oxygen vacancies with a positive charge are diffused to the undoped terminal, resulting in an increase in the width of $W_1$; thus, the resistance status of the device becomes low, as $R_{ON}$ [27]. Conversely, the resistance increases with $R_{OFF}$. Hereby, a SPICE model with a definite hysteresis curve and threshold is proposed, as in Equation (1), for generalized memristor devices [28], where $a_1$, $a_2$ and b are real factors, and $I\left(t\right)$ and $V\left(t\right)$ are the current and voltage, respectively.

$$I\left(t\right)=\left\{\begin{array}{c}{a}_{1}x\left(t\right)sinh\left(bV\left(t\right)\right),V\left(t\right)\ge 0\hfill \\ a_{2}x\left(t\right)sinh\left(bV\left(t\right)\right),V\left(t\right)\le 0\hfill \end{array}\right.$$

(1)

$x\left(t\right)$ in Formula (2) is written as

$$\frac{dx}{dt}=\eta g\left(V\left(t\right)\right)f\left(x\left(t\right)\right)$$

(2)

where $\eta$ determines the positive and negative polarity of the voltage, and $g\left(V\right(t\left)\right)$ is expressed as

$$g\left(V\left(t\right)\right)=\left\{\begin{array}{c}{A}_p(e^{V\left(t\right)}-e^{V_p}),V\left(t\right)>V_p\hfill \\ -A_n\left(e^{(-V(t)}\right)-e^{V_n}),V\left(t\right)<-V_n\hfill \\ 0,-V_n\le V\left(t\right)\le V_p\hfill \end{array}\right.$$

(3)

where $V_p$ and $V_n$ are positive and negative threshold voltages, and $A_p$ and $A_n$ are adjustable amplitudes. $f\left(x\right)$ is the following expression, $w_n$ and $w_p$ are window functions, and $x_n$ and $x_p$ are state values near the negative and positive ends of the memristor, respectively.

$$f\left(x\right)=\left\{\begin{array}{c}{e}^{-{\partial }_p(x-x_p)w_p(x,x_p)},x\ge x_p\hfill \\ 1,x\le x_p\hfill \end{array}\right.$$

(4)

$$f\left(x\right)=\left\{\begin{array}{c}{e}^{{\partial }_n(x+x_n-1)w_n(x,x_n)},x\le 1-x_n\hfill \\ 1,x>1-x_n\hfill \end{array}\right.$$

(5)

This model is simulated in LTspice, and its hysteresis curve is shown in Figure 2. The parameters of the model defined for the simulation are listed in

Table 1. Parameters of the memristor model.

Parameter	${\mathit{a}}_1$	${\mathit{a}}_2$	b	${\mathit{V}}_{\mathit{p}}$	${\mathit{V}}_{\mathit{n}}$	${\mathit{A}}_{\mathit{p}}$	${\mathit{A}}_{\mathit{n}}$	${\mathit{x}}_{\mathit{p}}$	${\mathit{x}}_{\mathit{n}}$
Value	0.12	0.12	0.05	0.16	0.15	30,000	30,000	0.3	0.3

.

2.2. Logic Gates Based on Memristor

The performance of logic circuits can be improved efficiently by MRL based on nanoscale memristors. Some logic gates, such as NOR and NAND, have been implemented utilizing MRL [18]. Herein, the inverters in the logic gates are designed using MOS transistors with 50 nm BSIM4 models [26]. Supposing that $V_{high}=1$, $V_{low}=0$, as shown in Figure 3a, if A = 1 and B = 0, then the output of memristor $V_1$ is

$$V_1=\frac{R_{OFF}}{R_{ON}+R_{OFF}}{V}_{high}=1$$

(6)

When $V_1=1$, PMOS transistor $T_2$ is cut off and NMOS $T_1$ is switched on. Therefore, the output of the NOR gate $V_{out}=0$. Analogously, when input signals A and B take other values, the corresponding outputs are consistent with the logic truth table of the NOR gate. The working process of the NAND is roughly the same. The simulation results of the logic gates displayed in Figure 4 are in agreement with the corresponding truth table.

3. DFF Design

3.1. Design of Level DFF Circuit

Based on the NOR and NAND gates, two structures of a DFF are designed, as displayed in Figure 5a,b, respectively, where (a) is a low-level flip-flop and (b) is a high-level flip-flop. The simulation results obtained when they are implemented in LTspice are illustrated in Figure 6. The output Qs of these two DFFs vary with the input Ds when the clock input is low and high, respectively, as shown in Figure 6a,b.

The simulation results demonstrate the feasibility of DFFs based on memristors. However, the level-triggered mode may cause the DFF to flip several times during the effective clock signal, leading to a weak anti-interference ability. Therefore, DFFs with an edge-triggered mode are designed below to improve the reliability and anti-interference ability.

3.2. Design of Edge DFF Circuit

Two edge-triggered DFFs with master and slave latches have been designed, as shown in Figure 7. These DFFs are effectively triggered by the falling edge and rising edge of the clock signal, respectively, as illustrated in Figure 8a,b.

Table 2. Master–slave DFF truth table based on NOR and NAND gates.

	CLK	D	Q
NOR	*	0	maintain
		1
	↓ (falling edge)	0	set 0
		1	set 1
NAND	•	0	maintain
		1
	↑ (rising edge)	0	set 0
		1	set 1

describes the functions of these DFFs (* denotes times other than the falling edge; • indicates times other than the rising edge). These DFFs have also been implemented and simulated in LTspice, and the simulation results are depicted in Figure 8.

The master–slave DFFs above consist of two identical flip-flops; each has a two-stage inversion structure. Therefore, the master flip-flop’s output can be fed back to the input and the constructed NOR memristors can be combined to simplify the structure of the circuit, resulting in more area and energy efficiency. Furthermore, the proposed DFFs maintain the blocking characteristics during maintenance, as shown in Figure 9. The simulation results of these DFFs, illustrated in Figure 10, are consistent with the truth table presented earlier. The improved DFFs have 3 fewer memristors and 10 fewer CMOS transistors than their predecessors.

Table 3. Improved parameters of DFFs.

Design	Input Voltage (V)	Power ($\mathsf{\mu }$W)	Delay (ns)	Memristor	MOSFET
DFF (NOR)	1	44.72	0.497	13	12
DFF (NAND)	1	41.96	0.508	13	12

shows the parameters for the improved DFFs.

To verify the proposed DFFs’ feasibility, two test circuits are designed by connecting LEDs as loads to their outputs. The circuit and simulation results are shown in Figure 11 and Figure 12, respectively, where (a) and (b) are triggered at the falling edge and the rising edge, respectively.

The simulation results show that the LEDs light up when the outputs of the DFFs are high.

4. Linear Feedback Shift Register Design

Registers are critical components in digital sequential circuits and are in high demand in processors. Although latches are usually used to store bit data, flip-flops entail a large area and power overhead. As very important high-speed storage components, registers temporarily store instructions, data and addresses and are widely applied in various digital systems and microcontrollers. Figure 13 shows the two structures of a 4-bit linear feedback shift register (LFSR) mainly designed via the aforementioned improved DFFs. The driving equation and the state equation of the two 4-bit LFSRs are defined in Equations (7) and (8), respectively. Both of these DFFs have an identical state transition diagram (STD), as shown in Figure 14. Each DFF of the 4-bit LFSR is triggered at each falling edge of clk, as shown in Figure 15a. However, input D does not change immediately due to the transmission delay between the time that the falling edge of clk arrives and the established time of the new state of a DFF. Consequently, the state of the subsequent DFF varies according to the original Q state of the previous DFF. The final result is that all the initial codes in the 4-bit LFSR are shifted one bit to the right at each falling edge of clk. Figure 15b shows that the DFF is triggered at the rising edge of clk. The simulation results of the two 4-bit LFSRs shown in Figure 15 are consistent with the STD in Figure 14.

$$\left\{\begin{array}{c}{D}_0=Q_0\oplus Q_3\hfill \\ D_i=Q_{i-1}(i=1,2,3)\hfill \end{array}\right.$$

(7)

$$\left\{\begin{array}{c}{Q}_0^{*}=Q_0\oplus Q_3\hfill \\ Q_i^{*}=Q_{i-1}(i=1,2,3)\hfill \end{array}\right.$$

(8)

The functionality of the proposed register circuits is verified through LTSpice simulations carried out with the settings listed in

Table 4. Simulation settings.

Technology	Supply Voltage	Timestep	Temperature	Default Integration Method
50 nm	1 V (based on NOR/NAND)	0.1 $\mathsf{\mu }$s	27 °C	modified trap

. The comparison results of the partial existing LFSRs and the ones proposed in this work are demonstrated in

Table 5. Comparison of different works.

Design	Ref. [30]	Ref. [29]	Ref. [23]	This Work (NOR)	This Work (NAND)
Delay (ns)	0.813	−	0.841	0.551	0.583
Input Voltage (V)	1.8	1.8	4	1	1
Memristor	0	0	64	56	56
MOSFET	318	81	64	50	50
Power ($\mathsf{\mu }$W)	9360	188	94.15	63.4	62.8
Power Delay Product ($\mathsf{\mu }$J)	7.609	−	0.079	0.035	0.037

, where the power delay product (PDP) effectively demonstrates the characteristics of circuit power consumption and delay. It represents the product of power consumption and the delay time. The smaller the PDP, the better the working performance of the circuit. The two LFSRs reported in refs. [29,30], engineered with the traditional MOS transistors, require an excessive number of devices, resulting in high power consumption and a long delay time. The LFSR reported in ref. [23] is more energy-efficient than the former ones, although it employs 64 memristors and transistors. In contrast, the two LFSRs proposed herein optimize both the number of devices and the power consumption.

5. Application of LFSR in Built-In Self-Test

With the increasing scale and complexity of ICs, the built-in self-test (BIST) has become an indispensable part of circuit and chip design. Direct testing methods rely on automatic test equipment (ATE) to detect the circuit under test (CUT), which can be expensive and time-consuming. Under the BIST test mode, these challenges can be overcome. The architecture block diagram of the traditional BIST scheme is shown in Figure 16 and consists of test pattern generation (TPG), the circuit under test (CUT), an output response analyzer (ORA) and a BIST controller. The TPG comprises an n-bit LFSR (as shown in Figure 17 with C_i = 1, C_i = 0 and L_i indicating connection, disconnection and logical operation, respectively) that generates pseudo-random test vectors that are supplied to the CUT. The output signal of the CUT is then received and detected by the ORA module.

Herein, a logic BIST (LBIST) approach is designed for self-testing logic circuits. Specifically, a 16-bit LFSR is implemented to generate a large number of pseudo-random test vectors in each cycle, which are then provided to the CUT module for testing. The TPG is composed of the 16-bit LFSR as displayed in Figure 18. The simulation results of the 16-bit LFSR are depicted in Figure 19.

A simple 4-bit ORA is designed to simulate the process of receiving and checking the output signal of the CUT. The simulation results of this 4-bit ORA are presented in Figure 20. In this figure, V(1), V(2), V(3) and V(4) represent the output results of the CUT, and V(out) is the output of this ORA. It is obvious that the 4-bit ORA is a parity checker, and V(out) is of a high level when the number of “1”s in V(1) to V(4) is odd, and low otherwise.

6. Conclusions

In this paper, the design method for a memristor proportional logic circuit is adopted to realize a register based on a memristor–CMOS hybrid circuit. First, level-triggered DFFs are designed using NAND and NOR gates based on memristors, and two edge-triggered DFFs are implemented while applying the master–slave structure. Then, two simplified edge-triggered DFFs are proposed, utilizing the signals transmitted in the two-stage inversion. Compared to the reported designs, the new edge-triggered DFFs require fewer devices. Two new 4-bit LFSRs are engineered based on these DFFs and verified by simulation. In comparison to the partial existing LFSRs, this work improves the performance of the LFSR by reducing the number of devices significantly, decreasing the power consumption by 32.7% and 33.3% and optimizing the delay time by 34.5% and 30.7% for the NOR- and NAND-gate-based LFSRs, respectively. Finally, the proposed DFF triggered at the falling edge of the clock is applied to realize the main function of the BIST circuit, and a simulation is implemented to verify its correctness and feasibility.