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Article

A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters

1
National Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
2
University of Chinese Academy of Sciences, Beijing 100049, China
3
Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
*
Author to whom correspondence should be addressed.
Electronics 2023, 12(24), 5042; https://doi.org/10.3390/electronics12245042
Submission received: 21 November 2023 / Revised: 14 December 2023 / Accepted: 14 December 2023 / Published: 18 December 2023
(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

Abstract

:
This paper proposes a fully digital background calibration method for time-interleaved analog-to-digital converter (TIADC) mismatches. The method analyzes the frequency and phase of spurious signals caused by three types of mismatches in TIADCs in the frequency domain. By utilizing the Hilbert transform and frequency shifting, orthogonal basis signals located at the mismatch frequencies can be constructed. The calibration of mismatches is achieved by linearly combining the orthogonal basis signals with the estimated coefficients and subtracting them from the original signal. The estimation of coefficients is determined by evaluating the correlation between the linear combination of orthogonal basis signals and the calibrated signal. Furthermore, an exponential moving average (EMA) and least mean square (LMS) algorithm are introduced to expedite the coefficient estimation process. The entire calibration process converges in merely 600 samples, significantly improving the convergence speed. By monitoring the amplitude of the input signal and adjusting the LMS step, the algorithm is functional under different amplitude signals, enhancing the robustness. An off-chip calibration is conducted based on a commercial 14-bit, 8-channel, 2.4GSPS TIADC. Results indicate that all spurious signals are suppressed below 80 dB, and the convergence rate is consistent with the simulation.

1. Introduction

With the advancement of communication technology and semiconductor technology, high-speed and high-precision ADCs are widely used in radar, software radio, base stations, and other fields [1,2]. Despite the increasing performance requirements of electronic systems for analog-to-digital converters (ADCs), it is difficult for a single-chip ADC to simultaneously meet the requirements for both speed and precision due to limitations in the manufacturing process and circuit architecture. TIADCs utilize alternate sampling of multiple high-precision but lower-speed sub-ADCs to achieve high-speed sampling for the entire ADC system [3,4,5]. However, due to factors such as chip processing and manufacturing, temperature, and voltage variations, there are mismatches between different sub-ADCs, resulting in an inconsistent sampling behavior of each sub-ADC. The main mismatches of the TIADC include offset mismatch, gain mismatch, and timing mismatch, which can all severely degrade the dynamic performance of the TIADC. Therefore, the original sampling data need to be calibrated for reducing the spurious signal caused by these mismatches.
The common calibrations for offset and gain mismatches first need to accumulate and average the input signal and then subtract it from the original signal. This method is simple and effective, but it requires a large amount of data for computation, resulting in a slower convergence speed [6,7,8].
With the progress of advanced processes, clock frequencies and channel counts are continually increasing, whereas the performance deterioration originating from the timing mismatch becomes the main challenge. Thus, many studies focus on the timing calibration methods, which can be divided into hybrid and digital circuit calibrations. The hybrid calibration method estimates the magnitude of the mismatches through digital circuits and uses analog circuits with variable delay lines (VDLs) or delay loop locks to compensate and adjust for the mismatches [9,10,11,12]. However, analog circuits have poor portability, and the VDLs vary with different manufacturing processes, temperature, and voltage variations. In addition, controlling the switching of sampling channels in TIADC using random sequences generated by digital circuits can effectively eliminate periodic spurs caused by timing mismatches [13,14]. However, this method increases the noise floor and cannot effectively improve the signal-to-noise ratio (SNR).
In the calibration of digital circuits, based on variations in calibration algorithm principles, two distinct types can be identified: time-domain calibration and frequency-domain calibration. The time-domain calibration methods estimate and compensate different mismatches in turn. Hereunto, the derivative filter is a conventional timing mismatch compensation method, which can be compensated within a small mismatch range [15,16,17,18,19]. For a large mismatch, a derivative filter with higher order is necessary, causing a rapid increase in resource consumption. The Farrow structure-based fractional delay filter is also a commonly used compensation method, but its performance will deteriorate seriously when the input signal frequency is high [20]. Reconstructed filter banks can effectively calibrate the mismatched signal, but the circuit structure is complicated [21,22]. In time-domain calibration methods, three mismatches of offset, gain, and timing are generally calibrated in order. These methods have residual errors after each calibration, thus affecting the accuracy of the next calibration. In terms of convergence speed, the successive calibration needs to wait for the convergence of the estimated values by three mismatches one by one, resulting in a long time requirement.
As the aforementioned counterpart, the frequency-domain calibration method is generally based on the spectrum method. The Hilbert transform is used to construct the mismatched signal and subtract it from the original signal [23]. The genetic algorithm, as another commonly used estimation method of mismatches, is rarely applied to background calibration [24]. Inverse Fourier transform [25] and the polynomial estimation of channel response [26] can also be employed to calibrate the mismatches. However, there is a clear penalty for high complexity, slow convergence speed, and low compatibility with varied amplitudes of input signals in these traditional calibration methods based on the frequency domain.
In this paper, we propose a new frequency domain calibration method that can simultaneously calibrate three key types of mismatch (i.e., offset, gain, and timing mismatches), rather than calibrating them one by one. The orthogonal base signal is generated by the input signal and the linear coefficient is estimated to be subtracted from the original signal to calibrate the mismatches. By introducing a variable step LMS algorithm that emulates the effect of an adjustable low-pass filter, fast convergence can be achieved at any amplitude to meet the needs of some fast convergence applications. And for larger mismatches, this calibration method can also be completed well.

2. TIADC Model and Mismatch Analysis in the Frequency Domain

2.1. Mismatch Model of TIADC

The M channel TIADC uses M sub-ADCs to sample with equal intervals and output sequentially. Figure 1 shows the structure of the M-channel TIADC. The sampling period of the sub-ADC is M T s , when the period of the TIADC is T s . For an ideal TIADC, the output of the m-th sub-ADC is
y m [ n ] = x [ ( n M + m ) · T s ] , m = 0 , 1 , , M 1 ,
where x is the signal to be sampled.
The sampling clock phase of each sub-ADC is evenly distributed in the clock cycle of a TIADC; that is, the phase deviation of two adjacent subADCs is T s , as shown in Figure 2.
Considering the mismatches, the m-th sub-ADC can be expressed as
y m [ n ] = x n M + m + Δ t m · T s · 1 + Δ g m + Δ o m .
The Δ o m , Δ g m , Δ t m represent offset mismatch, gain mismatch, and timing mismatch of the m-th channel, respectively. The transfer function of the m-th channel is
H m j ω = 1 + Δ g m · e j ω ( m + Δ t m ) frequency-dependent + Δ o m · δ j ω frequency-independent ,
where δ j ω is a Dirac function, indicating that the offset mismatch exists only at zero frequency in the frequency domain. The right side of Equation (3) can be divided into two parts, one is the input signal frequency-dependent term (FDT), which is composed of gain and timing mismatches. The other part is the frequency-independent term (FIT), which is composed of offset mismatch.
As shown in Figure 1, the M channel interleaving of the TIADC can be regarded as the sum of M-times up-sampling. And thus, the periodic spurious signal caused by up-sampling will appear at ω s p u r on the spectrum.
ω s p u r = ω i n + n M ω s , n = 1 , 2 , , M 1 .
Take the case of a four-channel TIADC; the spectrum of the sub-ADC before and after four-time up-sampling is shown in Figure 3.
Considering up-sampling and mismatches, the discrete-time Fourier transform (DTFT) of each sub-ADC can be expressed as
Y m e j ω = 1 M n = 0 M 1 e j 2 π m n M H m e j ( ω 2 π n / M ) m - ch frequency response X e j ( ω 2 π n / M ) input signal , m = 0 , 1 , , M 1 .
The sampling data of the 0-th channel at the frequency domain can be obtained by
Y 0 ( e j ω ) = 1 4 n = 0 M 1 H 0 e j ω 2 π n 2 π n 4 4 X e j ω 2 π n 2 π n 4 4 = 1 4 H 0 e j ω X e j ω + H 0 e j ω 2 π 2 π 4 4 X e j ω 2 π 2 π 4 4 + H 0 e j ω 2 π · 2 2 π · 2 4 4 X e j ω 2 π · 2 2 π · 2 4 4 + H 0 e j ω 2 π · 3 2 π · 3 4 4 X e j ω 2 π · 3 2 π · 3 4 4 .
The sub-ADC0 consists of four groups of frequency components, which are the product of the frequency response of the sub-ADC0 with the up-sampled input signal. The up-sampling and mismatches do not change the signal frequency, so the DTFT of each sub-ADC is similar to Figure 3. The k-th component of the m-th channel can be represented as
S m k = H m e j ω 2 π k 2 π k 4 4 X e j ω 2 π k 2 π k 4 4 .
Then, the DTFT of subADCs in the four-channel TIADC can be represented as
4 · Y 0 = S 0 0 + S 0 1 + S 0 2 + S 0 3 , 4 · Y 1 = S 1 0 + S 1 1 · e j 2 π 4 + S 1 2 · e j 2 π · 2 4 + S 1 3 · e j 2 π · 3 4 , 4 · Y 2 = S 2 0 + S 2 1 · e j 2 π · 2 4 + S 2 2 · e j 2 π · 4 4 + S 2 3 · e j 2 π · 6 4 , 4 · Y 3 = S 3 0 + input signal S 3 1 · e j 2 π · 3 4 spur 1 + S 3 2 · e j 2 π · 6 4 spur 2 + S 3 3 · e j 2 π · 9 4 spur 3 .
Similar to Y 0 , the first item of Y m represents the original input signal, and the other items represent spur s 1 , s 2 , and s 3 . There is no phase shift in the four signal components of Y 0 , but the phases of the other terms in Y m are different except for the first term representing the input signal. Since the amplitude spectrum of Figure 3 do not exclude phase information, the amplitude spectrum of each sub-ADC is similar to Figure 3.
In Equation (8), the horizontal direction represents different sub-channels, while the vertical direction represents different frequency components of the signal. Since the TIADC is the vector sum of M sub-ADCs, it can not only decompose the signal based on sub-ADCs but also be based on different frequency components. By combining the same frequency components of each sub-ADC in the vertical direction, M groups of frequency components S k can be obtained, which can be represented as
S k e j ω = m = 0 M 1 e j 2 π m k M · S m k e j ω = m = 0 M 1 e j 2 π m k M H m e j ω 2 π k 2 π k M M X e j ω 2 π k 2 π k M M , k = 0 , 1 , , M 1 .

2.2. The Input Signal Component

The first group of frequency components S 0 of the sub-ADCs are all located at the input signal position and can be expressed as
S 0 e j ω = 1 M m = 0 M 1 S 0 m = 1 M m = 0 M 1 H m e j ω X e j ω .
Ideally, the sampling behavior of each sub-ADC is completely consistent, with the same frequency response H m = 1 . At this time, S 0 can be expressed as
S 0 e j ω = X e j ω .
Taking M = 4 as an example, the mean of four vectors with the same amplitude and phase is the same as that of the scalars. The vector sum of FDT or FIT can be shown in Figure 4a.
When considering the mismatches, S 0 is
S 0 e j ω = 1 M m = 0 M 1 1 + Δ g m · X e j ω · e j ω Δ t m FDT + 1 M m = 0 M 1 Δ o m · δ j ω · X e j ω FIT .
The right side of Equation (12) consists of the FDT and FIT. On one hand, the amplitude and phase mismatch of the M groups of frequency components that are related to the input signal will result in small phase and amplitude deviations in the vector sum compared to the original input. For the output of the TIADC, the small amplitude and phase deviations do not affect the dynamic performance of the ADC. The FDT with four different phase amplitudes can be represented as shown in Figure 4b. On the other hand, the mismatches caused by the FIT will lead to a small spurious signal at zero frequency, that is, a small DC signal.

2.3. The Remaining Frequency Components

Except for the input signal components S 0 , the remaining frequency components, S k , are unwanted signals, which are the spurious signals. Due to the phase interval of the sampling clock, the phase of each sub-ADC is different at the same frequency component in S k .
Without the mismatches, the frequency response of each sub-ADC is the same, and S k can be expressed as
S k e j ω = 1 M m = 0 M 1 e j 2 π m k M · X e j ω 2 π k 2 π k M M , k = 1 , , M 1 .
Similarly, the S 1 component of the four-channel TIADC is described as
S 1 e j ω = 1 M X e j ω 2 π 2 π k 4 4 + e j 2 π 4 X e j ω 2 π 2 π k M M + e j 4 π 4 X e j ω 2 π 2 π k M M + e j 6 π 4 X e j ω 2 π 2 π M M .
As shown in Figure 5a, when there are no mismatches, and S 1 contains four identical frequency components with the same amplitude and phase, which is uniformly distributed over a 2 π period. Therefore, the vector sum of these four components is zero, meaning that S 1 is zero and S k for k > 0 .
Considering the mismatches, S k is
S k e j ω = 1 M m = 0 M 1 1 + Δ g m · X e j ( ω 2 π k / M ) · e j 2 π m k M + ω · Δ t m + 1 M m = 0 M 1 Δ o m · δ ( j ( ω 2 π k / M ) ) · X e j ( ω 2 π k / M ) .
And S 1 can be expressed as
S 1 e j ω = 1 M 1 + Δ g 0 · e j ω Δ t 0 · X e j ( ω 2 π / 4 ) + 1 + Δ g 1 · e j 2 π 4 ω Δ t 1 · X e j ( ω 2 π / 4 ) + 1 + Δ g 2 · e j 4 π 4 ω Δ t 2 · X e j ( ω 2 π / 4 ) + 1 + Δ g 3 · e j 6 π 4 ω Δ t 3 · X e j ( ω 2 π / 4 ) + 1 M m = 0 M 1 Δ o m · δ ( j ( ω 2 π / 4 ) ) · X e j ( ω 2 π / 4 ) .
Due to the influence of gain and timing mismatches, the signal amplitude and phase of the FDT in Equation (16) will undergo slight changes. As shown in Figure 5b, the changes in the frequency components of the four sub-ADCs result in a non-zero vector sum, which is equivalent to any signal with arbitrary amplitude and phase at that frequency. This vector sum signal acts as spurious signals in the output spectrum of the TIADC, as shown by s 1 in Figure 6b. Similarly, the FIT will introduce a spurious signal o k caused by offset mismatch at frequency ω offset = 2 π n / M .
Figure 6 shows a comparison between the ideal spectrum of a four-channel TIADC and the appearance of spurious signals due to the mismatches.

2.4. Orthogonal Decomposition of Spur Signal

According to the orthogonal decomposition theorem, any signal with arbitrary amplitude and phase can be decomposed into a linear combination of two phase-orthogonal signals with the same frequency. As shown in Figure 7, the two orthogonal signals are respectively referred to as I k and Q k .
In other words, by constructing orthogonal basis signals and linearly combining them with appropriate coefficients, the spurious signal S k can be obtained by
S k e j ω = w s k I · I s k + w s k Q · Q s k + w o k I · I o k + w o k Q · Q o k = w s k I · X e j ω 2 π n 2 π n M M + w s k Q · X e j ω 2 π n 2 π n M M · e j π 2 + w o k I · δ j ω 2 π n 2 π n M M + w o k Q · δ j ω 2 π n 2 π n M M · e j π 2 ,
where I s k and Q s k ( I o k and Q o k ) represent the two orthogonal basis signals of the FDT (FIT). The w represents the coefficient corresponding to the orthogonal basis component.
y ^ [ n ] = y [ n ] k = 0 M 1 y ^ k f d [ n ] k = 0 M 1 y ^ k f i [ n ] = y [ n ] y s k I / Q [ n ] × w ^ s k I / Q y o k I / Q [ n ] × w ^ o k I / Q .

3. The Proposed Calibration Method and Hardware Structure

As shown in Figure 8, by multiplying the estimated orthogonal basis coefficients with the orthogonal basis signals and subtracting them from the original sampled signal, it is possible to simultaneously calibrate the three types of mismatches.

3.1. Orthogonal Basis Signals Generation

3.1.1. Principle of Generating Orthogonal Basis Signals

From the above analysis, it can be seen that a TIADC with M channels has M groups of frequency components. The first group S 0 of the input signals is the desired signal. The remaining groups are undesired signal components introduced by mismatches, which need to be constructed and compensated. Therefore, the orthogonal basis signal at frequency ω s p u r needs to be generated, and the coefficients of the orthogonal basis signal need to be estimated for linear combination.
Firstly, the sampled signal is transformed by Hilbert transform and combined with the original sampled signal to obtain the analytical signal y a ; that is, the bilateral spectrum of the real signal is changed into the unilateral spectrum:
y a [ n ] = y [ n ] + j · y _ h i l b [ n ] .
Then, the analytic signal y a is frequency-shifted by e j 2 π k 2 π k M M to generate M-1 groups of signals at frequencies ω s p u r , and the k-th frequency-shifted signal is
y s k [ n ] = y a [ n ] · e j 2 π k n 2 π k M M .
According to Euler formula:
e j ( 2 π k n / M ) = cos ( 2 π k n / M ) + j · sin ( 2 π k n / M )
Obviously, the frequency of the real part of the signal is the same as that of the imaginary part, and the real part is the derivative of the imaginary part. According to the trigonometric function, the phase of the real part and imaginary part is orthogonal. Therefore, the signal is separated into its real and imaginary parts, which form a pair of orthogonal basis signals. The orthogonal basis signals are represented as y s k I and y s k Q signals:
y s k I = Re y a · e j ( 2 π k n / M ) = y [ n ] · cos ( 2 π k n / M ) y hilb [ n ] · sin ( 2 π k n / M ) , y s k Q = Im y a · e j ( 2 π k n / M ) = y [ n ] · sin ( 2 π k n / M ) + y hilb [ n ] · cos ( 2 π k n / M ) .
Figure 9 shows the spectral changes of the orthogonal base signals generated from the input signal.
The FIT only has frequency shift components, so the k-th group of the orthogonal basis can be expressed as
y o k I [ n ] = cos ( 2 π k n / M ) , y o k Q [ n ] = sin ( 2 π k n / M ) .

3.1.2. Multi-Phase Structure of Orthogonal Basis Signal Generation

In the TIADC, the low-speed ADC of M channels is used to sample alternately to obtain the sampling signals of M sub-ADCs. The M channel data can be considered as the M-phase data of the TIADC. When implementing filters in digital circuits, it is also necessary to use polyphase filters to process multi-phase data. The unit impulse response of the Hilbert filter is given by
h ( t ) = 1 / π t .
For filters that require multi-phase processing, it is preferable for the order to be an integer multiple of 2 M . A 32-order polyphase FIR Hilbert filter is recommended to improve accuracy, and a Hamming window to the coefficients is applied to reduce truncation effects. The 32-order filter without polyphase processing is expressed as
y _ h i l b [ n ] = k = 0 32 h [ k ] · y [ n k ] .
In the 32-order polyphase filter, the 0-th phase sub-filter is
y _ h i l b 0 [ n ] = y _ h i l b [ 4 n ] = k = 0 32 h [ k ] · y [ 4 n k ] = h [ 0 ] · y [ 4 n ] + h [ 1 ] · y [ 4 n 1 ] + + h [ 32 ] · y [ 4 n 32 ] .
The m-th phase filter can be expressed as
y _ h i l b m [ n ] = y _ h i l b [ 4 n + m ] = k = 0 32 h [ k ] · y [ 4 n k + m ] .
The Hilbert FIR filter is antisymmetric, and when the total order is even, half of the coefficients of the Hilbert filter are zero. After folding and coefficient optimization, the 4-phase filter is expressed as:
y _ h i l b m [ n ] = y _ h i l b [ 4 n + m ] = k = 0 7 h [ 2 k ] · y 4 n 2 k + m y 32 4 n 2 k + m .
The structure of the four-phase Hilbert filter is shown in Figure 10. The data from the four sub-ADCs pass through a four-phase delay chain and then through four sub-filters.
The specific structure of the delay chain is shown in the Figure 11. The number of stages of the shift register is the order of the filter T a p s / M , where the tapped output after each delay is used by four sub-filters.
The FIR sub-filter using a folding structure is shown in Figure 12. Since the even coefficients are all 0, each sub-filter requires only eight multipliers.
According to Equation (22), after undergoing the Hilbert transform, the input signal further requires multiplication with a trigonometric function sequence for frequency shifting. Analogously, this trigonometric function sequence corresponds to the orthogonal basis signals of the FIT.
y o 1 I [ n ] = cos ( 2 π n / 4 ) = [ 1 , 0 , 1 , 0 , ] , y o 1 Q [ n ] = sin ( 2 π n / 4 ) = [ 0 , 1 , 0 , 1 , ] y o 2 I [ n ] = cos ( 4 π n / 4 ) = [ 1 , 1 , 1 , 1 , ] , y o 2 Q [ n ] = sin ( 4 π n / 4 ) = 0 , y o 3 I [ n ] = cos ( 6 π n / 4 ) = [ 1 , 0 , 1 , 0 , ] , y o 3 Q [ n ] = sin ( 6 π n / 4 ) = [ 0 , 1 , 0 , 1 , ] .
From Equation (29), the trigonometric function sequence is periodic with a period of M. In the hardware implementations of multi-phase processing, each phase datum corresponds to a fixed set of coefficients. Therefore, when the constant coefficients are 1, −1, and 0, the multipliers can be omitted, thereby reducing hardware resources. The process of generating the I and Q orthogonal basis signals can be represented by Figure 13.
The orthogonal basis coefficients of the FIT are inherent to Equation (29). Obviously, y o 1 I = y o 3 I , y o 1 O = y o 3 O , and y o 2 Q = 0 . Therefore, for the four-channel TIADC, there are six orthogonal basis coefficients to be calculated, and only three need to be calculated after optimization. For the polyphase coefficient generation circuit, the period of each orthogonal basis sequence is M, so the k-th group of m-th phase orthogonal basis coefficients is
y o k , m I / Q = y o k I / Q [ m ] .
The frequency-dependent k-th component can be expressed as
y k f d = w ^ s k I · y s k I + w ^ s k Q · y s k Q = w ^ s k I · m = 0 M 1 y s k , m I + w ^ s k Q · m = 0 M 1 y s k , m Q .
And the k-th FIT component can expressed as
y k f i = w ^ o k I · y o k I + w ^ o k Q · y o k Q = w ^ o k I · m = 0 M 1 y o k , m I + w ^ o k Q · m = 0 M 1 y o k , m Q .
Figure 14 is the recommended mismatch compensation circuit. The orthogonal base signal generated by the input signal is multiplied by the corresponding coefficient to obtain the mismatch signal estimation value.
In the polyphase correction circuit, the data for each phase need to be subtracted separately and can be expressed as
y ^ m [ k ] = y m [ k ] m = 1 M 1 w ^ s k I · y s k , m I + w ^ s k Q · y s k , m Q m = 1 M 1 w ^ o k I · y o k , m I + w ^ o k Q · y o k , m Q .

3.2. Estimation Method of Orthogonal Basis Coefficients

3.2.1. Orthogonal Basis Coefficient Estimation Structure

The structure of the coefficient estimation is shown in Figure 15. The cross-correlation C o r s k I / Q between the compensated signal y ^ and its orthogonal basis signal y ^ s k I / Q is taken as the error signal.
C o r s k I / Q = CORR y ^ s k I / Q , y ^ .
The coefficients of the orthogonal basis can be obtained by iterating the error function through the LMS algorithm. Fundamentally, LMS is a type of adaptive filter; however, when a small μ is employed, the resultant coefficients w ^ I / Q k can be considered as a smoothing process of the input C o r , similar to the effect of a low-pass filter.
w ^ I / Q k [ n ] = w ^ I / Q k [ n 1 ] + μ · C o r s k I / Q [ n ] ,
μ is the step length.
In the initial stage of calibration, there are mismatch signals in y ^ , and the orthogonal basis signal y ^ s k I / Q and y ^ have strong correlation. At this time, the cross-correlation C o r s k I / Q is large. As the calibration progresses, the mismatch signal in y ^ is gradually compensated, and the correlation C o r s k I / Q gradually decreases, and the estimated value of the coefficient w ^ I / Q k [ n ] gradually converges.
The correlation function is realized by the cascade of multiplication and exponential moving average (EMA), as shown in Figure 16. The coefficient of EMA is N, which can be expressed as:
A v e [ n ] = N 1 N · A v e [ n 1 ] + 1 N · d [ n ] = ( 1 α ) · A v e [ n 1 ] + α · d [ n ] .
In multi-phase processing, M data should be accumulated and averaged in each cycle, so the traditional EMA is not applicable. A multi-phase EMA is proposed that can perform the cumulative average of M data simultaneously, which is equivalent to M data entering the EMA sequentially. Figure 17 illustrates the structure of the multi-phase EMA.
The calculation of cross-correlation can be expressed as:
C o r s k I / Q = CORR y ^ s k , m I / Q , y ^ m = lim N 1 N + 1 n = 0 N m = 0 M 1 y ^ s k , m I / Q [ n ] · y ^ m [ n ] .
The input data manifest as M phases, with each phase being composed of M frequency components. Following phase shifting, every frequency component is multiplied individually with the calibrated y ^ . Subsequently, the distinct phase signals with the unified frequency are amalgamated, and the mean value is computed through the EMA methodology. Ultimately, the estimation of coefficients is obtained via the LMS approach. Figure 18 shows the frequency-dependent orthogonal basis coefficient estimation circuit structure.
From Equations (30) and (32), the estimated circuit structure of the four-phase frequency-independent orthogonal basis coefficients can be obtained as shown in Figure 19.

3.2.2. Adaptive Step Adjustment Method

From Equation (36), the transfer function of the EMA can be obtained as
H ( z ) = 1 z N N · 1 1 z 1 .
Obviously, the EMA is a low-pass filter. When the EMA coefficient N is determined, the amplitude of the input signal determines the amplitude of the EMA output. Figure 20 shows the output signal amplitude of EMA at different input signal amplitudes.
As the amplitude of the input signal increases, the steady-state error of the EMA output signal becomes larger and larger. The LMS for calculating the coefficient utilizes the date output by the EMA. From the Equation (35), it can be seen that the LMS is essentially a low-pass filter, and the step μ determines the filtering ability of the LMS. As the μ increases, the output of the LMS becomes smoother, but the convergence of coefficients becomes slower.
In the four-channel 14-bit ADC, the EMA coefficient N = 6 . At different input signal amplitudes, Figure 21a,b respectively depict the calibrated SNR and spurious-free dynamic range (SFDR) obtained with varying LMS coefficients μ .
In order to acquire the appropriate coefficients at any amplitude fast, a method of dynamically adjusting the μ by detecting the amplitude of the input signal is proposed. By detecting the amplitude of the input signal, the step μ can be dynamically adjusted. When the magnitude is large, a larger μ is used to improve the accuracy, otherwise, a smaller μ is used to improve the convergence speed. In 14-bit TIADCs, the corresponding relationship between the quantized step μ and the adjustment interval of the input signal amplitude is
μ = 33 , A m p > 1 dB 32 , 3 dB < A m p < 1 dB 31 , 6 dB < A m p < 3 dB 30 , 9 dB < A m p < 6 dB 29 , 12 dB < A m p < 9 dB 28 , A m p < 12 dB .

4. Experimental Result

4.1. Simulation Result

To verify the effectiveness of the proposed calibration method, a four-channel 14-bit TIADC model is established. Offset mismatch is modeled as [ 0.01 , 0.018 , 0.024 , 0.005 ] of the input signal amplitude. The ratio of the gain mismatch to the input signal amplitude is [ 0.01 , 0.04 , 0.02 , 0.03 ] . Timing mismatch is modeled as [ 0 , 0.01 , 0.02 , 0.015 ] · T s .
Figure 22 is the spectrum before and after calibration when the input signal frequency is 0.43 f s and the amplitude is 3 dB. The five spurious signals caused by offset, gain, and timing mismatches are well suppressed. The SNR and SFDR are improved from 25.11 dB and 28.09 dB to 79.95 dB and 109.3 dB, respectively.
Figure 23 shows the convergence process of the orthogonal basis coefficients. All orthogonal basis coefficient converge before 600 sampling points.
Figure 24 shows the SNR results before and after calibration at different input signal amplitudes and frequencies. Due to the adaptive step μ , the convergence speed of the orthogonal basis remains consistent under different amplitudes, requiring only around 600 points. Moreover, TIADC mismatches at different input signal frequencies can be effectively compensated.
The spectrum before and after calibration is shown in Figure 25, indicating that the method still effectively compensates for the three mismatches, and the calibration method is also applicable to a wide mismatch range. In brief, this method can not only be used for channel mismatch calibration within a chip but also for system-level mismatch calibration between multiple chips.
To verify the efficacy of our calibration method under the some extreme case, we enlarge the set values of the three mismatches to as high as five times than the initial set values.

4.2. Hardware Implementation and Validation

Based on the commercial eight-channel 14-bit TIADC from SIMCHIP, the off-chip calibration is performed on the FPGA using the recommended method. FPGA is VC707 from Xilinx, and JESD204B interface is used for signal transmission between the TIADC and FPGA. The input signal was a 2.5 GHz sine wave with a sampling frequency of 2.4 GSPS. Figure 26 is the test platform composed of the TIADC chip and FPGA circuit board.
Figure 27 shows the spectrum before and after calibration. It is evident that the seven frequency-related spurs and four offset mismatches have been effectively suppressed, with an increase in SNR from 37.86 to 51.61 and SFDR from 41.98 to 77.58 dB. Due to the influence of the second harmonic and the third harmonic, the mismatch signal cannot be completely eliminated.
Figure 28 shows the convergence process of the orthogonal basis coefficients during the calibration process. The entire calibration process converges around 2000 sampling points. Additionally, the mismatch coefficients can quickly follow fluctuations caused by mismatches due to thermal noise, voltage, temperature variations, and other factors.
Table 1 presents the comparative results of the SNR and SFDR before and after calibration using FPGA when sampling different input signal frequencies with the TIADC chip. This demonstrates that the calibration method can effectively enhance the dynamic performance of the TIADC across various frequencies. Despite fluctuations in the SFDR metric due to the influence of third-order harmonics and higher-order harmonics, the overall efficacy of the calibration remains evident.
Table 2 presents the hardware resource utilization of the calibration circuits synthesized and implemented on the VC707 for both four-channel and eight-channel TIADCs.
Table 3 compares the recommended calibration methods with the popular calibration methods in recent years. Many methods only involve timing mismatch calibration, and the traditional gain mismatch calibration method is very time-consuming. The proposed method can not only calibrate offset, gain, and timing mismatches at the same time, but the whole calibration process is also much faster than other methods.

5. Conclusions

This article recommends a fast background mismatch calibration method for TIADCs. By constructing orthogonal basis signals of the input signal and quickly estimating the coefficients of the orthogonal basis signals based on correlation functions and the LMS algorithm, it is possible to effectively calibrate all three mismatches of the TIADC simultaneously. With an amplitude-adaptive step size, the coefficients can converge quickly at any amplitude. The simulation of a four-channel model and the off-chip calibration of a commercial eight-channel TIADC have verified the calibration accuracy and convergence speed of this method.

Author Contributions

Conceptualization, L.S. and Y.D.; methodology, L.S.; software, L.S., L.L. and W.Z.; validation, W.Z., L.L. and H.L.; formal analysis, L.L.; investigation, L.S. and W.Z.; resources, L.S. and Y.D.; data curation, L.L. and H.L.; writing—original draft preparation, L.S.; writing—review and editing, L.L., W.Z. and H.L.; visualization, L.S. and L.L.; supervision, Y.D.; project administration, Y.D.; funding acquisition, Y.D. and L.L. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Research Foundation of the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant XDA18030100, and was funded by the Shanghai Sailing Program under Grant 22YF1456400.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. The structure of M channel TIADC.
Figure 1. The structure of M channel TIADC.
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Figure 2. The sampling clock of four-channel TIADC and sub-ADCs.
Figure 2. The sampling clock of four-channel TIADC and sub-ADCs.
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Figure 3. The spectrum of sub-ADC. (a) Spectrum of sub-ADC without up-sampling; the red line represents the input signal. (b) Spectrum of sub-ADC with up-sampling; s 1 , s 2 and s 3 are spurious signals at ω s p u r .
Figure 3. The spectrum of sub-ADC. (a) Spectrum of sub-ADC without up-sampling; the red line represents the input signal. (b) Spectrum of sub-ADC with up-sampling; s 1 , s 2 and s 3 are spurious signals at ω s p u r .
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Figure 4. The vector sum of FDT or FIT in S 0 . (a) The vector sum of the S 0 component of the four sub-ADCs without mismatches. (b) The vector sum of the S 0 component of the four sub-ADCs with mismatches.
Figure 4. The vector sum of FDT or FIT in S 0 . (a) The vector sum of the S 0 component of the four sub-ADCs without mismatches. (b) The vector sum of the S 0 component of the four sub-ADCs with mismatches.
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Figure 5. The vector sum of S 1 . (a) The vector sum of the S 1 component of the four sub-ADCs without mismatches. (b) The vector sum of the S 1 component of the four sub-ADCs with mismatches.
Figure 5. The vector sum of S 1 . (a) The vector sum of the S 1 component of the four sub-ADCs without mismatches. (b) The vector sum of the S 1 component of the four sub-ADCs with mismatches.
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Figure 6. The spectrum of TIADC. (a) Spectrum of TIADC without mismatches; the signal represents the input signal. (b) Spectrum of TIADC with mismatches. s k are spurious signals caused by FDT. o k are spurious signals caused by FIT.
Figure 6. The spectrum of TIADC. (a) Spectrum of TIADC without mismatches; the signal represents the input signal. (b) Spectrum of TIADC with mismatches. s k are spurious signals caused by FDT. o k are spurious signals caused by FIT.
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Figure 7. The orthogonal decomposition (i.e., I k and Q k ) of the spurious signal S k . These two orthogonal signals with the same frequency are combined linearly.
Figure 7. The orthogonal decomposition (i.e., I k and Q k ) of the spurious signal S k . These two orthogonal signals with the same frequency are combined linearly.
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Figure 8. The structure of mismatch calibration.
Figure 8. The structure of mismatch calibration.
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Figure 9. The spectral changes of the orthogonal base signals generated from the input signal. (a) The spectrum of original input. (b) The spectrum of analytic signal composed by Hilbert transform. (c) The analytic signal spectrum shifted to three corresponding frequencies. (d) The real or imaginary part of the spectrum.
Figure 9. The spectral changes of the orthogonal base signals generated from the input signal. (a) The spectrum of original input. (b) The spectrum of analytic signal composed by Hilbert transform. (c) The analytic signal spectrum shifted to three corresponding frequencies. (d) The real or imaginary part of the spectrum.
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Figure 10. The structure of 4-phase Hilbert filter.
Figure 10. The structure of 4-phase Hilbert filter.
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Figure 11. The delay chain structure of 4-phase 32-order Hilbert filter.
Figure 11. The delay chain structure of 4-phase 32-order Hilbert filter.
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Figure 12. The structure of 4-phase 32-order Hilbert sub-filter.
Figure 12. The structure of 4-phase 32-order Hilbert sub-filter.
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Figure 13. The circuit structure of orthogonal basis signal generation.
Figure 13. The circuit structure of orthogonal basis signal generation.
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Figure 14. The structure based on FDT and FIT mismatch compensation method.
Figure 14. The structure based on FDT and FIT mismatch compensation method.
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Figure 15. The structure of the coefficient estimation.
Figure 15. The structure of the coefficient estimation.
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Figure 16. The structure of EMA and cross-correlation.
Figure 16. The structure of EMA and cross-correlation.
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Figure 17. The structure of multi-phase EMA.
Figure 17. The structure of multi-phase EMA.
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Figure 18. The structure of frequency-dependent polyphase orthogonal basis coefficient estimation.
Figure 18. The structure of frequency-dependent polyphase orthogonal basis coefficient estimation.
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Figure 19. The structure of frequency-independent polyphase orthogonal basis coefficient estimation.
Figure 19. The structure of frequency-independent polyphase orthogonal basis coefficient estimation.
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Figure 20. The output signals of the EMA when the input signal amplitude is −1 dB and −9 dB, respectively.
Figure 20. The output signals of the EMA when the input signal amplitude is −1 dB and −9 dB, respectively.
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Figure 21. Under different input signal amplitudes, the SNR and SFDR results of the calibrated TIADC as a function of μ in LMS. (a) The SNR comparison before and after calibration under different amplitude input signals. (b) The SFDR comparison before and after calibration under different amplitude input signals.
Figure 21. Under different input signal amplitudes, the SNR and SFDR results of the calibrated TIADC as a function of μ in LMS. (a) The SNR comparison before and after calibration under different amplitude input signals. (b) The SFDR comparison before and after calibration under different amplitude input signals.
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Figure 22. The spectrum of four-channel 14-bit TIADC before and after calibration when the input signal frequency is 0.43 f s , with an amplitude of 3 dB. (a) Before calibration: the spurious signals caused by FDT appear in the spectrum of 0.07 f s , 0.18 f s and 0.32 f s . The spurious signals caused by FIT appear in the 0.25 f s and 0.5 f s . (b) After calibration: all the spurious signals are eliminated except for the input signal at 0.43 f s .
Figure 22. The spectrum of four-channel 14-bit TIADC before and after calibration when the input signal frequency is 0.43 f s , with an amplitude of 3 dB. (a) Before calibration: the spurious signals caused by FDT appear in the spectrum of 0.07 f s , 0.18 f s and 0.32 f s . The spurious signals caused by FIT appear in the 0.25 f s and 0.5 f s . (b) After calibration: all the spurious signals are eliminated except for the input signal at 0.43 f s .
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Figure 23. The convergence process of four-channel TIADC orthogonal basis coefficients. (a) FDT orthogonal basis coefficients. (b) FIT orthogonal basis coefficients.
Figure 23. The convergence process of four-channel TIADC orthogonal basis coefficients. (a) FDT orthogonal basis coefficients. (b) FIT orthogonal basis coefficients.
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Figure 24. Calibration under different input signal amplitude. (a) SNR before and after calibration under different input signal amplitudes. (b) The convergence time of orthogonal basis coefficients.
Figure 24. Calibration under different input signal amplitude. (a) SNR before and after calibration under different input signal amplitudes. (b) The convergence time of orthogonal basis coefficients.
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Figure 25. In the case of large mismatches, the spectrum before and after calibration when the input signal is 0.43 f s . (a) Before calibration: the SNR of the spectrum before calibration is only 25.1 dB, and the SFDR is 28.1 dB. (b) After calibration: the other spurious signals are suppressed below the noise floor except for the input signal.
Figure 25. In the case of large mismatches, the spectrum before and after calibration when the input signal is 0.43 f s . (a) Before calibration: the SNR of the spectrum before calibration is only 25.1 dB, and the SFDR is 28.1 dB. (b) After calibration: the other spurious signals are suppressed below the noise floor except for the input signal.
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Figure 26. TIADC off-chip calibration test platform.
Figure 26. TIADC off-chip calibration test platform.
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Figure 27. The spectrum diagram before and after off-chip calibration. (a) The spectrum before calibration shows that the 8-channel TIADC has 7 frequency-dependent spurs and 4 frequency-independent spurs. (b) The spectrum after calibration, all the spurious are calibrated in 80 dB.
Figure 27. The spectrum diagram before and after off-chip calibration. (a) The spectrum before calibration shows that the 8-channel TIADC has 7 frequency-dependent spurs and 4 frequency-independent spurs. (b) The spectrum after calibration, all the spurious are calibrated in 80 dB.
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Figure 28. The convergence of out-of-chip calibration partial orthogonal basis coefficients. (a) The convergence process of seven frequency-dependent orthogonal basis coefficients. (b) The convergence process of seven frequency-independent orthogonal basis coefficients.
Figure 28. The convergence of out-of-chip calibration partial orthogonal basis coefficients. (a) The convergence process of seven frequency-dependent orthogonal basis coefficients. (b) The convergence process of seven frequency-independent orthogonal basis coefficients.
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Table 1. Dynamic performance comparison before and after off-chip FPGA calibration at various input signal frequencies with the input signal amplitude of 3 dB.
Table 1. Dynamic performance comparison before and after off-chip FPGA calibration at various input signal frequencies with the input signal amplitude of 3 dB.
Input Signal Frequency 0.041 f s 0.11 f s 0.145 f s 0.312 f s 0.4 f s
SNR Bef Cali (dBFS) 43.1 dB 43.2 dB 44.2 dB 44.2 dB 42.6 dB
SNR Aft Cali (dBFS) 58.1 dB 57.6 dB 57.6 dB 56.6 dB 55.7 dB
SFDR Bef Cali (dBFS) 46.9 dB 46.7 dB 46.3 dB 46.1 dB 46.6 dB
SFDR Aft Cali (dBFS) 75.2 dB 74.1 dB 70.1 dB 70.5 dB 69.4 dB
Table 2. Hardware resource utilization of calibration circuits implemented on FPGA.
Table 2. Hardware resource utilization of calibration circuits implemented on FPGA.
ResourceUtilization (4-Channel)Utilization (8-Channel)Available
LUT527 (0.17%)952 (0.31%)303,600
FF829 (0.14%)1113 (0.18%)607,200
DSP58 (2.07%)177 (6.32%)2800
Table 3. Comparison of the state-of-the-art calibration methods.
Table 3. Comparison of the state-of-the-art calibration methods.
Characteristics[15][25][26]This Work
BackgroundYesNoYesYes
MethodologySimplify Matrix MultiplicationInverse Discrete Fourier TransformPolynomial FittingOrthogonal Decomposition
Channels44164 & 8
Resolution1212Data14
Arbitrary ChannelYesYesYesYes
Matrix operationYesNoNoNo
Mismatch TypeTimingOffset, Gain, TimingGain, TimingOffset, Gain, Timing
Type-by-Type CalibrationYesNoNoNo
Conve.Time (sample#)110k+10 M1.2 M600
SFDR/SNR (improvement)38 dB/25 dB22 dB/8dB40 dB/-36 dB/14 dB
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Sun, L.; Lang, L.; Zhong, W.; Liu, H.; Dong, Y. A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters. Electronics 2023, 12, 5042. https://doi.org/10.3390/electronics12245042

AMA Style

Sun L, Lang L, Zhong W, Liu H, Dong Y. A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters. Electronics. 2023; 12(24):5042. https://doi.org/10.3390/electronics12245042

Chicago/Turabian Style

Sun, Lin, Lili Lang, Wei Zhong, Haijing Liu, and Yemin Dong. 2023. "A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters" Electronics 12, no. 24: 5042. https://doi.org/10.3390/electronics12245042

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