Modeling and Experimental Validation of Dual-Output Flyback Converters with Capacitive Coupling for Improved Cross-Regulation

Abstract

This paper addresses cross-regulation in dual-output flyback converters. An original analytical framework is developed to model the impact of a balancing capacitor connected among a transformer’s secondary windings in order to mitigate the cross-regulation among different outputs. To validate the proposed model, a prototype dual-output flyback converter was built and tested for a wide range of load unbalances. The measured cross-regulation error was compared with the theoretical predictions provided by the proposed model, obtaining a tight fit, which confirms the validity of the proposed approach.

1. Introduction

In the evolving domain of industrial electronics, the flyback converter stands out as a prominent topology for low-power applications, renowned for its galvanic isolation, minimal component count, wide output voltage range, ease of control, and cost-effectiveness [1,2,3,4,5,6,7]. The inherent isolation significantly contributes to the development of multi-output DC-DC power converters, which are essential for a variety of applications, including computing, television, telecommunications, and battery charging systems. Despite their widespread adoption [8,9], multi-output flyback converters face significant challenges in achieving effective cross-regulation, attributed to their complex dynamics and component non-idealities [10]. This phenomenon implies that variations in the load current of any output terminal result in corresponding changes in the output voltage of other terminals [11,12,13]. The leading factors contributing to cross-regulation include leakage inductances, along with transformer winding resistances and diode voltage drops. These elements collectively result in deviations in output voltages when load unbalances occur across different outputs [13,14,15,16].

A wide range of strategies, from post-regulation to active and passive solutions, was explored to mitigate the cross-regulation issue [10,12]. However, while post-regulation approaches may offer a straightforward solution for achieving tightly regulated outputs, they come with significant drawbacks. Linear post-regulators, even when employing low-dropout technology, are subject to considerable power losses that adversely affect overall system efficiency. On the other hand, switching post-regulators, despite their potential for higher efficiency, contribute to increased component count and system complexity, presenting challenges in design and integration [11,17]. Alternatively, active strategies use advanced techniques, such as replacing or augmenting output diodes with active switching devices for improved regulation [18,19]. Several configurations using multiple transformers have also been proposed to improve cross-regulation [20,21,22]. However, active approaches significantly increase complexity and component count, challenging the balance between regulation, efficiency, and power density.

Conversely, passive methods aim to enhance regulation without increasing complexity, by transformer winding optimization [23] or by using stacked transformer windings and stacked outputs [24,25]. While these methods can reduce cross-regulation, they may complicate the implementation of synchronous rectification. The weighted-feedback method spreads the error across all outputs, trading off precision for reduced cross-regulation [26,27].

Capacitive coupling, a straightforward passive technique involving capacitors connected across output pairs, has found application in multi-output flyback converters, where the output voltages are equal in magnitude [28].

Despite its common usage, there is a notable absence of a detailed analytical framework in the literature that directly links the amplitude of cross-regulation with load imbalances. Addressing this gap, this study aims to establish a comprehensive model of a dual-output flyback converter featuring capacitive coupling under unbalanced output current loads. The interplay between leakage inductances, bridging capacitors, and their impact on output cross-regulation is thoroughly analyzed.

Section 2 details an analytical approach for deriving the converter model, elucidating the inherent mechanism for cross-regulation in flyback converters and examining its critical factors. Section 3 presents the experimental results obtained by characterizing a prototype built to validate the derived key points.

2. Dual-Output Flyback Converter

A flyback converter cyclically stores energy in its transformer from the input DC source when its switch is on and subsequently delivers this stored energy to its outputs after the switch is turned off. By adjusting the amount of energy stored and released per cycle, the output voltage can be regulated. Figure 1 illustrates a typical two-output flyback converter topology featuring a zener-diode.

In Figure 1 is represented the transformer model with a magnetizing inductance, $Lm$; and equivalent leakage inductances $L_{kp}$, $L_{k1}$, and $L_{k2}$; along with winding resistances $R_{wp}$, $R_{w1}$, and $R_{w2}$, corresponding to those of the primary and secondary windings, respectively. The turns ratios of the secondary windings with respect to the primary winding are $n_1$ and $n_2$ values, respectively. In standard flyback converters, when the load on output 2 of the converter is different from that on output 1, a voltage mismatch arises, mainly due to the transformer’s output leakage inductances [12,13]. To address this issue, a balancing capacitor, $C_C$, is introduced between the two transformers’ output windings [28]. This capacitor provides an alternative discharge path for excess current from the lightly loaded output’s secondary winding to the more heavily loaded output. For this solution to effectively enhance cross-regulation, it is crucial that the $C_C$ capacitor’s terminals are connected between secondary windings exhibiting similar waveforms. This requirement specifies equal turns on both output windings. Additionally, a balanced dual-output voltage topology can be achieved by connecting the positive terminal of one output to the ground and keeping the balancing capacitor across the anodes of both output rectifying diodes.

In the analytical modeling, the forward voltage of the output rectifier diodes $D_{O1}$ and $D_{O2}$ is initially neglected. Furthermore, to simplify the analysis, the primary winding leakage inductance $L_{kp}$ is neglected in calculations, as its primary effect lies in the energy transferred to the secondary side [29]. Its impact on output cross-regulation is thus minimal, and can eventually be reintroduced at a later stage for converter gain calculation. Conversely, the coupling between the output windings significantly influences the output voltage, as it is determined by the current through different windings and the leakage inductances [24,30]. Consequently, leakage inductance in the secondary sides of the transformer directly affects the cross-regulation under unbalanced load conditions.

Analytical Modeling

The load current ratio between the two outputs can be expressed as $m={\displaystyle \frac{I_{O2}}{I_{O1}}}$. In a steady state, circuit currents and voltages remain constant, allowing us to estimate their averages over multiple switching periods. Specifically, we find it convenient to consider m + 1 periods. Due to the presence of the $C_C$ capacitor, it is convenient to model the operation of the circuit by assuming that for m periods current flows towards the output 1 through diode $D_{O1}$, and for one period towards the lightly loaded output 2 through diode $D_{O2}$. It is important to note that this model can be deemed valid if the balancing capacitor $C_C$ is selected to be sufficiently large, ensuring that the resonance frequency of the series equivalent circuit comprising the leakage inductances $L_{k1}$, $L_{k2}$, and $C_C$ is significantly lower than the switching frequency $f_s$. This prerequisite is essential for enabling the series circuit to act as a capacitive impedance, thereby establishing a low-impedance pathway for the flow of the balancing current.

$$f_r={\displaystyle \frac{1}{2\pi \sqrt{(L_{k1}+\frac{1}{m}{L}_{k2})·C_C}}}\ll f_s$$

(1)

Under this condition, the current waveforms of this model can be plotted for $m+1$ switching cycles, as illustrated in Figure 2, when operating in discontinuous conduction mode (DCM), without loss of generality. Likewise, the various subintervals can be identified as illustrated in Figure 3.

During the first subinterval of duration $D{T}_S$, as illustrated in Figure 3a, the switch $S_1$ is closed and the magnetizing current is increasing according to

$$\partial i_{Lm}\left(t\right)={\displaystyle \frac{Vin}{Lm}}\partial t$$

(2)

During this period, while the output rectifying diodes remain open, the output capacitors $C_{O1}$ and $C_{O2}$ discharge to supply respective outputs. Simultaneously, the balancing capacitor $C_C$ discharges through both secondary windings of the transformer. Given that the ratio between the two transformer secondary sides is ideally equal ($n_1=n_2=n$), the voltages on the secondary windings have identical amplitudes equal to the input voltage. Consequently, the $C_C$ balancing capacitor undergoes a discharge, which can be described as

$$\partial i_{Cc}\left(t\right)=\partial i_{L_{k2}}\left(t\right)=-\partial i_{L_{k1}}\left(t\right)={\displaystyle \frac{v_{Cc}\left(t\right)}{L_{k1}+L_{k2}}}\partial t$$

(3)

During the second subinterval of duration $D_2{T}_S$, as shown in Figure 3b, the switch $S_1$ opens, and the zener diode $Z_{SN}$ clamps the voltage on the transformer’s primary side to the zener voltage $V_Z$. Consequently, the magnetizing current decreases according to

$$\partial i_{Lm}\left(t\right)=-{\displaystyle \frac{V_Z}{nLm}}\partial t$$

(4)

During this subinterval, we can distinguish between the times when the output diode $D_{O1}$ is in conduction (${\displaystyle \frac{m}{m+1}}$ times) and when the output diode $D_{O2}$ is in conduction (${\displaystyle \frac{1}{m+1}}$ times). When $D_{O1}$ conducts, the balancing capacitor $C_C$ redirects the current from the secondary winding of output 2 to output 1. Both windings reflect the clamped voltage $V_Z$ multiplied by the turn ratio n. The current through $C_C$ can be expressed as a function of the output voltages and the voltage across $C_C$ itself.

$$\partial i_{Cc}\left(t\right)=-\partial i_{L_{k2}}\left(t\right)=-{\displaystyle \frac{n{V}_Z-V_{O1}+v_{Cc}\left(t\right)}{L_{k2}}}\partial t$$

(5)

Meanwhile, the leakage inductance on the secondary winding of output 1 charges according to

$$\partial i_{L_{k1}}\left(t\right)={\displaystyle \frac{n{V}_Z-V_{O1}}{L_{k1}}}\partial t$$

(6)

Moreover, the capacitor on output 2 sustains the output current $I_{O2}$ by itself, whereas the capacitor on output 1 also receives the current flowing through the output diode $D_{O2}$.

$$\partial i_{C_{O1}}\left(t\right)=[{\displaystyle \frac{n{V}_Z-V_{O1}}{L_{k1}}}+{\displaystyle \frac{n{V}_Z-V_{O1}+v_{Cc}\left(t\right)}{L_{k2}}}-I_{O1}]\partial t$$

(7)

When the output diode $D_{O2}$ conducts, the balancing capacitor $C_C$ redirects the current from the secondary winding of output 1 to output 2. The current through $C_C$ can now be expressed as

$$\partial i_{Cc}\left(t\right)=\partial i_{L_{k1}}\left(t\right)=-{\displaystyle \frac{n{V}_Z-V_{O2}-v_{Cc}\left(t\right)}{L_{k1}}}\partial t$$

(8)

Meanwhile, the leakage inductance on the secondary winding of output 2 charges according to

$$\partial i_{L_{k2}}\left(t\right)={\displaystyle \frac{n{V}_Z-V_{O2}}{L_{k2}}}\partial t$$

(9)

This time, the capacitor on output 1 sustains the output current entirely by itself, while the capacitor on output 2 also receives the current flowing through the output diode $D_{O2}$.

$$\partial i_{C_{O2}}\left(t\right)=[{\displaystyle \frac{n{V}_Z-V_{O2}}{L_{k2}}}+{\displaystyle \frac{n{V}_Z-V_{O2}-v_{Cc}\left(t\right)}{L_{k1}}}-I_{O2}]\partial t$$

(10)

This subinterval ends when the current through the zener clamping diode drops to zero, after a decrease that equals the current reached by the magnetizing inductance during its charging, according to Equation (2). This can be expressed as

$${\displaystyle \frac{V_{IN}}{Lm}}D{T}_S-[{\displaystyle \frac{V_Z}{nLm}}+{\displaystyle \frac{n{V}_Z-V_{O1}}{L_{k1}}}+{\displaystyle \frac{n{V}_Z-V_{O2}}{L_{k2}}}]D_2{T}_S=0$$

(11)

During the third subinterval of duration $D_3{T}_S$, the primary side of the transformer is no longer clamped to the zener voltage. Consequently, a voltage $V_S$ is established across both the transformer secondary windings until the magnetizing inductance is completely discharged. Hence, the magnetizing current discharges according to

$$\partial i_{Lm}\left(t\right)=-{\displaystyle \frac{V_S}{nLm}}\partial t$$

(12)

During this subinterval, the behavior of the converter is the same as in the second subinterval for both ${\displaystyle \frac{1}{m+1}}$ and ${\displaystyle \frac{m}{m+1}}$ periods. Accordingly, the equations for $i_{L_{k1}}$, $i_{L_{k2}}$, $i_{C_C}$, $i_{C_{O1}}$, and $i_{C_{O2}}$, written for the second subinterval, still hold by replacing $V_Z$ with $V_S$.

Finally, during the fourth subinterval of duration $D_4{T}_S$, the magnetizing inductance $L_m$ is completely discharged, and no current flows through the primary side of the transformer. Similar to the first subinterval, the output capacitors $C_{O1}$ and $C_{O2}$ supply the load currents, while the balancing capacitor $C_C$ discharges through both secondary windings of the transformer, as described in Equation (3).

By considering the average values of all variables over $m+1$ switching periods, and making some simplifying assumptions, such as $L_{k1}=L_{k2}=L_k$ and $n=1$, it is possible to write the system of Equation (13).

$$\begin{array}{c}\hfill \left\{\begin{array}{c}{I}_{L_{k1}}={\displaystyle \frac{-V_{Cc}}{2L_k}}(D+D_4)+[m{\displaystyle \frac{V_Z-V_{O1}}{L_k}}+{\displaystyle \frac{V_Z-V_{O2}-V_{Cc}}{L_k}}]{\displaystyle \frac{D_2}{m+1}}+[m{\displaystyle \frac{V_S-V_{O1}}{L_k}}+{\displaystyle \frac{V_S-V_{O2}-V_{Cc}}{L_k}}]{\displaystyle \frac{D_3}{m+1}}=0\hfill \\ I_{L_{k2}}={\displaystyle \frac{V_{Cc}}{2L_k}}(D+D_4)+[m{\displaystyle \frac{V_Z-V_{O1}+V_{Cc}}{L_k}}+{\displaystyle \frac{V_Z-V_{O2}}{L_k}}]{\displaystyle \frac{D_2}{m+1}}+[m{\displaystyle \frac{V_S-V_{O1}+V_{Cc}}{L_k}}+{\displaystyle \frac{V_S-V_{O2}}{L_k}}]{\displaystyle \frac{D_3}{m+1}}=0\hfill \\ I_{C_{O1}}=-I_{O1}+{\displaystyle \frac{m}{m+1}}[{\displaystyle \frac{V_Z-V_{O1}}{L_k}}+{\displaystyle \frac{V_Z-V_{O1}+V_{Cc}}{L_k}}]D_2+{\displaystyle \frac{m}{m+1}}[{\displaystyle \frac{V_S-V_{O1}}{L_k}}+{\displaystyle \frac{V_S-V_{O1}+V_{Cc}}{L_k}}]D_3=0\hfill \\ I_{C_{O2}}=-I_{O2}+[{\displaystyle \frac{V_Z-V_{O2}}{L_k}}+{\displaystyle \frac{V_Z-V_{O2}-V_{Cc}}{L_k}}]{\displaystyle \frac{D_2}{m+1}}+[{\displaystyle \frac{V_S-V_{O2}}{L_k}}+{\displaystyle \frac{V_S-V_{O2}-V_{CC}}{L_k}}]{\displaystyle \frac{D_3}{m+1}}=0\hfill \\ I_{C_C}={\displaystyle \frac{-V_{Cc}}{2L_k}}(D+D_4)+[{\displaystyle \frac{V_Z-V_{O2}-V_{Cc}}{L_k}}-m{\displaystyle \frac{V_Z-V_{O1}+V_{Cc}}{L_k}}]{\displaystyle \frac{D_2}{m+1}}+[{\displaystyle \frac{V_S-V_{O2}-V_{Cc}}{L_k}}-m{\displaystyle \frac{V_S-V_{O1}+V_{Cc}}{L_k}}]{\displaystyle \frac{D_3}{m+1}}=0\hfill \\ I_{Z_{SN}}={\displaystyle \frac{Vin}{Lm}}D-[{\displaystyle \frac{V_Z}{Lm}}+{\displaystyle \frac{V_Z-V_{O1}}{L_k}}+{\displaystyle \frac{V_Z-V_{O2}}{L_k}}]D_2=0\hfill \\ I_{Lm}={\displaystyle \frac{Vin}{Lm}}D-{\displaystyle \frac{V_Z}{nLm}}{D}_2-{\displaystyle \frac{V_S}{nLm}}{D}_3{T}_S=0\hfill \end{array}\right.\end{array}$$

(13)

By calculating $I_{L_{k2}}-I_{L_{k1}}$, we obtain

$${\displaystyle \frac{V_{Cc}}{L_k}}(D+D_4)+{\displaystyle \frac{V_{Cc}}{L_k}}(D_2+D_3)=0$$

(14)

and by taking into account that $D+D_2+D_3+D_4=1$, it is determined that the average of $v_{C_C}\left(t\right)$ is

$$V_{Cc}=0$$

(15)

By deriving $D_2$ from Equation (13), substituting it into the other equations, and considering Equation (15), we can simplify the system of Equation (13) to obtain the system of Equation (16).

$$\left\{\begin{array}{c}{I}_{L_{k1}}=VinD-(V_{O1}{\displaystyle \frac{m}{m+1}}+V_{O2}{\displaystyle \frac{1}{m+1}})(D_3+{\displaystyle \frac{Vin}{V_Z}}D-{\displaystyle \frac{V_S}{V_Z}}{D}_3)=0\hfill \\ I_{C_{O1}}=-I_{O1}{\displaystyle \frac{m+1}{m}}{\displaystyle \frac{L_k}{2}}+VinD-V_{O1}(D_3+{\displaystyle \frac{Vin}{V_Z}}D-{\displaystyle \frac{V_S}{V_Z}}{D}_3)=0\hfill \\ I_{C_{O2}}=-I_{O2}(m+1){\displaystyle \frac{L_k}{2}}+VinD-V_{O2}(D_3+{\displaystyle \frac{Vin}{V_Z}}D-{\displaystyle \frac{V_S}{V_Z}}{D}_3)=0\hfill \\ I_{Z_{SN}}=VinD-[{\displaystyle \frac{1}{Lm}}+{\displaystyle \frac{2}{L_k}}-{\displaystyle \frac{V_{O1}}{V_Z{L}_k}}-{\displaystyle \frac{V_{O2}}{V_Z{L}_k}}](VinD-V_S{D}_3)=0\hfill \\ I_{C_C}=(1-m)VinD+(m{V}_{O1}-V_{O2})(D_3+{\displaystyle \frac{Vin}{V_Z}}D-{\displaystyle \frac{V_S}{V_Z}}{D}_3)=0\hfill \end{array}\right.$$

(16)

By computing $I_{C_C}+m{I}_{C_{O1}}$, we obtain

$$I_{O1}(m+1){\displaystyle \frac{L_k}{2}}-VinD+V_{O2}(D_3+{\displaystyle \frac{Vin}{V_Z}}D-{\displaystyle \frac{V_S}{V_Z}}{D}_3)=0$$

(17)

from which the expression for $V_{O2}$ can be derived.

$$V_{O2}={\displaystyle \frac{VinD-I_{O1}(m+1)\frac{L_k}{2}}{D_3+\frac{Vin}{V_Z}D-\frac{V_S}{V_Z}{D}_3}}$$

(18)

By substituting the obtained expression for $V_{O2}$ into $I_{C_C}$, we obtain

$$I_{O1}(m+1){\displaystyle \frac{L_k}{2}}-mVinD+m{V}_{O1}(D_3+{\displaystyle \frac{Vin}{V_Z}}D-{\displaystyle \frac{V_S}{V_Z}}{D}_3)=0$$

(19)

from which the expression for $V_{O1}$ can also be derived.

$$V_{O1}={\displaystyle \frac{mVinD-I_{O1}(m+1)\frac{L_k}{2}}{m(D_3+\frac{Vin}{V_Z}D-\frac{V_S}{V_Z}{D}_3)}}$$

(20)

Provided that the second terms in the numerators of expressions for $V_{O1}$ and $V_{O2}$ are negligible, for the sake of solving the system equations, we can neglect their difference and assume that $V_{O1}\approx V_{O2}=V_{O_{1,2}}$. Hence, we can write

$$V_{O_{1,2}}={\displaystyle \frac{VinD}{D_3+\frac{Vin}{V_Z}D-\frac{V_S}{V_Z}{D}_3}}$$

(21)

By substituting the obtained values for $D_2$, $V_{O1}$, and $V_{O2}$ into the $I_{Z_{SN}}$ equation, we can derive the expression for $D_3$.

$$D_3={\displaystyle \frac{VinD[2V_{Z}Lm-V_S(L_k+2Lm)]}{V_S(V_Z-V_S)(L_k+2Lm)}}$$

(22)

Thus, by substituting the derived expression for $D_3$ back into the derived expression for $V_{O1}$ (Equation (20)), we can obtain the expression for $V_S$.

$$V_S={\displaystyle \frac{2V_{O1}Lm}{L_k+2Lm}}$$

(23)

$$\left\{\begin{array}{c}{P}_{in}=Vin\langle i_{in}\left(t\right)\rangle =Vin{\displaystyle \frac{Qin}{T_S}}=Vin{\displaystyle \frac{\frac{1}{2}D{T}_S\frac{VinD{T}_S}{Lm}}{T_S}}={\displaystyle \frac{Vi{n}^2{D}^2{T}_S}{2Lm}}\hfill \\ P_{Z_{SN}}=V_Z\langle i_{Z_{SN}}\left(t\right)\rangle =V_Z{\displaystyle \frac{Q_Z}{T_S}}=V_Z{\displaystyle \frac{\frac{1}{2}{D}_2{T}_S\frac{VinD{T}_S}{Lm}}{T_S}}={\displaystyle \frac{Vin{V}_{Z}D{D}_2{T}_S}{2Lm}}\hfill \\ P_{out}=V_{O1}{I}_{O1}+V_{O2}{I}_{O2}=V_{O_{1,2}}(I_{O1}+I_{O2})\hfill \end{array}\right.$$

(24)

By imposing the power balance $P_{in}=P_{Z_{SN}}+P_{out}$, and expressing the averaged values for input and zener currents in terms of the overall charge Q flowing along an entire switching period $T_S$, we can achieve the set of Equation (24).

By substituting the obtained values for $D_2$ and $D_3$, it is finally possible to derive the expression for the duty cycle D as a function of all specified design parameters, which include the output voltages $V_{O_{1,2}}$, output currents $I_{O1}$ and $I_{O2}$, the zener diode clamping voltage $V_Z$, input voltage $V_{in}$, the switching frequency $f_s={\displaystyle \frac{1}{T_S}}$, and the magnetizing and leakage inductances $L_m$ and $L_k$, respectively.

$$D=\sqrt{{\displaystyle \frac{V_{O_{1,2}}(I_{O1}+I_{O2})(V_Z(L_k+2Lm)-2V_{O_{1,2}}Lm)}{(V_Z-V_{O_{1,2}})Vi{n}^2{T}_S}}}$$

(25)

In the general case where $L_{k1}\ne L_{k2}$, the set of equations can be similarly derived as in the system of Equation (2).

$$\left\{\begin{array}{c}{V}_{O2}={\displaystyle \frac{VinD-I_{O1}(m+1)\frac{L_{k1}{L}_{k2}}{L_{k1}+L_{k2}}}{D_3+\frac{Vin}{V_Z}D-\frac{V_S}{V_Z}{D}_3}}\hfill \\ V_{O1}={\displaystyle \frac{mVinD-I_{O1}(m+1)\frac{L_{k1}{L}_{k2}}{L_{k1}+L_{k2}}}{m(D_3+\frac{Vin}{V_Z}D-\frac{V_S}{V_Z}{D}_3)}}\hfill \\ D_3={\displaystyle \frac{VinD[V_{Z}Lm-V_S(\frac{L_{k1}{L}_{k2}}{L_{k1}+L_{k2}}+Lm)]}{V_S(V_Z-V_S)(\frac{L_{k1}{L}_{k2}}{L_{k1}+L_{k2}}+Lm)}}\hfill \\ V_S={\displaystyle \frac{V_{O_{1,2}}Lm}{\frac{L_{k1}{L}_{k2}}{L_{k1}+L_{k2}}+Lm}}\hfill \\ D=\sqrt{{\displaystyle \frac{V_{O_{1,2}}(I_{O1}+I_{O2})(V_Z(\frac{L_{k1}{L}_{k2}}{L_{k1}+L_{k2}}+2Lm)-2V_{O_{1,2}}Lm)}{(V_Z-V_{O_{1,2}})Vi{n}^2{T}_S}}}\hfill \end{array}\right.$$

(26)

Since the balancing capacitor has a zero-mean voltage over a switching period (Equation (15)), the two output voltages can be considered equal, as shown in Equation (21). However, if the voltage drops $V_{D_{O1}}\left(I_{O1}\right)$ and $V_{D_{O2}}\left(I_{O2}\right)$ across the output rectifying diodes are taken into account, even with a null average voltage on the balancing capacitor $C_C$, a voltage difference is actually expected to appear on the output nodes, due to the unbalanced currents on rectifying diodes. Accordingly, it is possible to write

$$\left\{\begin{array}{c}{V}_{O1}=\langle v_x\left(t\right)\rangle -V_{D_{O1}}\left(I_{O1}\right)\hfill \\ V_{O2}=\langle v_y\left(t\right)\rangle -V_{D_{O2}}\left(I_{O2}\right)\hfill \end{array}\right.$$

(27)

Since $\langle v_x\left(t\right)\rangle =\langle v_y\left(t\right)\rangle$ owing to the zero average voltage across the $C_C$ balancing capacitor, we can write

$$V_{O2}=V_{O1}+V_{D_{O1}}\left(I_{O1}\right)-V_{D_{O2}}\left(I_{O2}\right)$$

(28)

Hence, the discrepancy in output voltages can be attributed directly to the voltage drops across the output rectifying diodes.

3. Experimental Section

The model outlined in Section 2 is assessed in this section by means of a prototype converter, providing double output at 17 V. The circuit schematic is depicted in Figure 4: a dual-positive output is obtained by a multi-winding transformer. One of the outputs, 17 V_FB, is regulated by means of a PMIC, whereas the other is left unregulated and is connected to the first one via a capacitor across the transformer secondary windings. A list of the main components utilized is reported in

Table 1. Circuit components.

Component	Manufacturer	Value
T1	Würth Elektronik	749196121
U1	Texas Instruments	LM51581
D3, D4, DSN	Vishay	V2PM10LHM3/H
TVS	Vishay	TPSMP24AHM3_A/H
$C_C$, C1, C5, C6	Samsung	CL21A226MAYNNNE

.

The selected transformer features a base winding inductance of 14.7 $\mathsf{\mu }$H, a typical leakage winding inductance of 210 nH, and a maximum winding DC resistance of 344 m$\Omega$. Under full load conditions, when both outputs provide +17 V at 250 mA, and the input voltage is +15 V, the primary DC current stabilizes at 0.72 A. To adhere to the specified maximum DC current rating of 0.55 A for each winding, two primary side windings are connected in parallel. This configuration ensures a maximum of 0.36 A on each winding, maintaining compliance with the winding DC current rating. The top and bottom sides of the experimental prototype are shown in Figure 5. Figure 5c assesses that the transformer temperature settles around 58.5 °C under full current load conditions.

Since two windings in parallel are used to drive the input of the transformer, its saturation current results to be 1.62 A. Consequently, an LM51581 from Texas Instruments was selected to close the loop and regulate the +17 V_FB output. This PMIC features a 1.63 A integrated power switch with a voltage rating of up to 85 V. The switching frequency was set close to 1 MHz to match the transformer’s maximum operating frequency. To limit the voltage on the drain of the LM51581’s integrated power switch within safe limits, a TVS diode clamp was implemented. Consequently, a TPSMP24AHM3_A/H TVS diode ensured that a maximum voltage smaller than 50 V was applied to the drain during switching intervals. Additionally, V2PM10LHM3/H Schottky diodes, boasting a rating of 100 V, 2 A, and a peak forward surge current of 50 A, were employed for both the clamping diode, $D_{SN}$, and the rectifying diodes, $D_{O1}$ and $D_{O2}$. Finally, the input, output, and balancing capacitors were 22 $\mathsf{\mu }$F, 25 V, and XR5 ceramic capacitors. A total capacitance of 88 $\mathsf{\mu }$F, achieved by connecting four capacitors in parallel, was placed on each output and on the input. Additionally, to filter out high-frequency spikes, two 100 nF capacitors were placed close to the input. The main circuit parameters are summarized in

Table 2. Main circuit parameters.

Parameter	Value	Parameter	Value
$f_S$	1 MHz	$L_{BASE}$	14.7 $\mathsf{\mu }$H
$V_{IN}$	15 V	$L_{k1}$	210 nH
$V_{OUT\_FB}$	17 V	$L_{k2}$	210 nH

.

This circuit with the parameters values discussed above and without the balancing capacitor $C_C$ exhibits a cross-regulation error that can exceed 20%, as shown in Figure 6.

The balancing capacitor $C_C$ mitigates this effect provided that it is chosen large enough to ensure that the resonance frequency of the series equivalent circuit comprising the leakage inductances $L_{k1}$, $L_{k2}$ and the balancing capacitor $C_C$ is significantly smaller than the switching frequency, as stated in Equation (1) in Section 2. This is necessary to enable the series circuit to operate as a capacitive impedance, thereby providing a low-impedance current path for forwarding the balancing current. Accordingly, a $C_C$ capacitance value of 22 $\mathsf{\mu }$F was used for establishing a frequency of approximately 74 kHz in the worst-case unbalanced scenario, corresponding to less than 1/10 of the switching frequency. The voltage rating of the capacitor was chosen to match the output voltages. In this case study, we used capacitors with the same voltage ratings for both the outputs and $C_C$.

It should be noted that for the circuit to operate properly, a minimum load must always be provided on the regulated output. Otherwise, the PMIC exhibits a random switching behavior. Consequently, no current is forced to flow through the balancing $C_C$ capacitor during the no-switching times, which invalidates the proposed model, as the unregulated output can no longer be balanced. Accordingly, the prototype tests are carried out with a minimum load of 5 mA applied on the regulated output, equivalent to the 2% of its maximum capability.

If both circuit outputs are loaded with the same current, the output voltages are balanced, as expected. The observed voltage difference between the +17 V and +17 V_FB outputs, as depicted in Figure 7, remains within a very small window, specifically between $0.059\%$ and $0.294\%$.

On the contrary, if the output currents are unbalanced, a small cross-regulation is observed, as shown in Figure 8c. The +17 V_FB voltage is regulated by the feedback loop of the PMIC LM51581 and remains constant for different load currents, except for some small drift, as shown in Figure 8a. In contrast, the voltage on the unregulated output decreases linearly with increasing output currents, as depicted in Figure 8b. To evaluate the cross-regulation regardless of the DC error on the regulated +17 V_FB output, it is useful to plot the offset between the two outputs, normalized to the voltage on the regulated output, as shown in Figure 8c. It is evident that the offset changes linearly with the load, according to the behavior depicted in Figure 8b. In particular, it becomes positive when the current on the unbalanced output is smaller than that on the regulated output, and vice versa. Notably, when the output currents are equal, the offset settles close to 0% for the different load points, as previously described in Figure 7.

In Section 2, the average voltage drop across the balancing capacitor $C_C$ was derived to be zero in a steady state. Experimentally, its voltage drop was measured with a 100 mA load on the regulated output and 50 mA on the unregulated one, and the acquired scope waveform is shown in Figure 9. The measured average voltage is smaller than 3 mV, which is negligible compared to the measured voltage offset of 210 mV observed in the results presented in Figure 8.

Accordingly, given that the $C_C$ capacitor keeps the circuital nodes (as depicted in Figure 1) at the same voltage, the offset observed between outputs in the presence of unbalanced loads can be directly related to the difference between the forward voltage drops of the output rectifying diodes, in the specific operating conditions (Equation (28)).

The circuit was simulated for the same load currents used for the experimental tests reported in Figure 8, solely considering output rectifying and snubber diodes, along with magnetizing and leakage inductances. The primary switch is the internal switch of the LM51581 PMIC, and was modeled as an ideal switch with a series resistance $R_{DS,on}$ of 150 m$\Omega$. A linearized model was considered for the diodes $D_1$, $D_2$, and $D_{SN}$ with a forward voltage drop of 0.6 V and a series resistance of 500 m$\Omega$; An ESR of 5 m$\Omega$ was considered for each 22 $\mathsf{\mu }$F capacitor. The simulation was carried out in an open loop with fixed duty cycles that were adjusted on the basis of the load conditions to achieve the desired output voltage.

The results are shown in Figure 10, where the dashed lines representing the simulation results are compared with the continuous lines representing the experimental points in Figure 8c. It can be observed that the simulation results are quite close with the measurements, which confirms the accuracy of the developed model.

4. Conclusions

This study introduces an original analytical framework to model a dual-output flyback converter with capacitive coupling to address the challenge of improving cross-regulation. The proposed model demonstrates that the voltage across the balancing capacitor can be considered null if its capacitance is properly chosen. Under these conditions, the cross-regulation directly relates to the different voltage drops of output diodes when different currents are flowing through them.

A prototype for a dual-output flyback was built, with only one output regulated and the other connected to the first by means of a capacitor across the secondary windings of the transformer. Measurements for the output voltages were carried out under various load conditions.

Comparison of the measured results with the simulated ones demonstrated a tight correlation. This assessed the validity of the proposed model and the conclusions drawn regarding the balancing mechanism and the factors affecting the residual cross-regulation.