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Semiconductor Packaging for the Age of Digitalization: New Materials, Technologies and Processes

A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Electronic Materials".

Deadline for manuscript submissions: closed (30 September 2021) | Viewed by 3385

Special Issue Editor


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Guest Editor
Faculty of Electrical Engineering and Information Technology, Technische Hochschule Ingolstadt (THI), Ingolstadt, Germany
Interests: metallic interconnect development; optoelectronic and sensor packaging; reliability analysis and lifetime prediction; condition monitoring; sensor data fusion and smart sensor systems

Special Issue Information

Dear Colleagues,

We are continuously observing new challenges in microelectronic packaging. Major trends like the Internet of Things, digitalization, and the application of Artificial Intelligence (AI) drive new requirements for hardware: new chip and system architecture, an increasing number of electric interconnects, low power consumption and miniaturization. In addition, autonomous intelligent systems such as self-driving cars will cause new challenges for functional safety, reliability, and lifetime prediction in the field of electronic devices. Cost-efficient methods for condition monitoring needs to be integrated on package level and realized on system level. Replacement, reusability, and recyclability of components and modules will become important for microelectronic packaging to approach the “0-failure vision” for complex systems within a sustainable and ecofriendly solution. Another major trend is the transition of energy supply and electrification, which affects microelectronic packaging. Power electronics, e.g., converters and electromobility, enable, in combination with wide gap semiconductors, high operation temperature under severe environmental conditions which are demanding for electronic materials, e.g., electrical and mechanical interconnect and encapsulation. The upcoming age of digitalization and Artificial Intelligence will be based on the hardware—based on new material, technologies, and packaging processes.

Prof. Dr. Gordon Elger
Guest Editor

Manuscript Submission Information

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Keywords

  • electrical and mechanical interconnects
  • advanced bonding methods and processes
  • wafer and panel level packaging
  • heterogeneous integration
  • redistribution and encapsulation
  • reliability and lifetime prediction

Published Papers (1 paper)

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Research

12 pages, 6703 KiB  
Article
Indium-Based Micro-Bump Array Fabrication Technology with Added Pre-Reflow Wet Etching and Annealing
by Paweł Kozłowski, Krzysztof Czuba, Krzysztof Chmielewski, Jacek Ratajczak, Joanna Branas, Adam Korczyc, Kazimierz Regiński and Agata Jasik
Materials 2021, 14(21), 6269; https://doi.org/10.3390/ma14216269 - 21 Oct 2021
Cited by 5 | Viewed by 2869
Abstract
Indium-based micro-bump arrays, among other things, are used for the bonding of infrared photodetectors and focal plane arrays. In this paper, several aspects of the fabrication technology of micrometer-sized indium bumps with a smooth surface morphology were investigated. The thermal evaporation of indium [...] Read more.
Indium-based micro-bump arrays, among other things, are used for the bonding of infrared photodetectors and focal plane arrays. In this paper, several aspects of the fabrication technology of micrometer-sized indium bumps with a smooth surface morphology were investigated. The thermal evaporation of indium has been optimized to achieve ~8 μm-thick layers with a small surface roughness of Ra = 11 nm, indicating a high packing density of atoms. This ensures bump uniformity across the sample, as well as prevents oxidation inside the In columns prior to the reflow. A series of experiments to optimize indium bump fabrication technology, including a shear test of single columns, is described. A reliable, repeatable, simple, and quick approach was developed with the pre-etching of indium columns in a 10% HCl solution preceded by annealing at 120 °C in N2. Full article
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