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Silicon Nanodevices
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Silicon Nanodevices

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (31 January 2022) | Viewed by 57893

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editors

Prof. Dr. Henry Radamson

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Guest Editor
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2. Guangdong Greater Bay Area Institute of Integrated Circuit and System, R&D Center of Optoelectronic Hybrid IC, Building A, No. 136 Kaiyuan Avenue, Development Zone, Guangzhou
3. University of Chinese Academy of Sciences, Beijing 100049, China
4. Mid Sweden University, Department of Electronics Design, Holmgatan 10, 85170 Sundsvall, Sweden
Interests: nanomaterials; nanoelectronics; nanophotonics; device processing; defects; strain engineering; CMOS; characterization; device physics; photodetectors; lasers; modulators; infrared; waveguides
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Guilei Wang

E-Mail Website
Guest Editor
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2. Guangdong Greater Bay Area Institute of Integrated Circuit and System, R&D Center of Optoelectronic Hybrid IC, Building A, No. 136 Kaiyuan Avenue, Development Zone, Guagnzhou
3. University of Chinese Academy of Sciences, Beijing 100049, China
Interests: nanomaterials; semiconductor processing and device physics; thin film deposition and epitaxy; material characterization; microelectronics; hererostructures; strain engineering; atomic layer deposition
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Nanodevices have attracted great attention in recent years due to their low power consumption and fast operation in electronics and photonics as well as high sensitivity in sensor applications. As an example, in following Moore’s law, the CMOS has undergone an evolution in design and architecture in integrated circuits. In principle, scaling down of the device structure can be performed by using advanced processing, but there are always different issues, e.g., concerning contact resistance, defects, and reliability, which can affect device performance. The current technology developments drive nanodevices towards 3D integration, and the merging of electronics and photonics is inevitable. Such designs will be the ultimate goal of nanotechnology in the future.  Therefore, this Special Issue will focus on the following scientific fields:

  • Fabrication and characterization of group IV nanostructures, nanodevices, and nanosensors
  • Carrier transport in nanodevices
  • Optoelectronic materials and nanodevices using Si-based heterostructures and nanostructures
  • Integration of photonics with Si CMOS technology
  • Strain bandgap engineering and carrier transport in CMOS
  • Si-based optical modulators, switches, and detectors
  • Si-based waveguide technology and nanodevices
  • Luminescence in Si-based materials
  • Integrated waveguide sensing
  • Nanomaterials for life science applications
  • Nanoscale biosensors
  • Defect engineering and characterization

This Special Issue creates unique knowledge for the readers in nanoscale physics, device processing, and material properties. 

Prof. Dr. Henry Radamson
Prof. Dr. Guilei Wang
Guest Editors

Manuscript Submission Information

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Keywords

  • nanomaterials
  • nanodevices
  • CMOS
  • device processing
  • nanosensors
  • nanophotonics
  • defects
  • characterization
  • strain

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Published Papers (13 papers)

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Editorial

Jump to: Research, Review

2 pages, 175 KiB  
Editorial
Special Issue: Silicon Nanodevices
by Henry H. Radamson and Guilei Wang
Nanomaterials 2022, 12(12), 1980; https://doi.org/10.3390/nano12121980 - 9 Jun 2022
Cited by 4 | Viewed by 1325
Abstract
In recent years, nanodevices have attracted a large amount of attention due to their low power consumption and fast operation in electronics and photonics, as well as their high sensitivity in sensor applications [...] Full article
(This article belongs to the Special Issue Silicon Nanodevices)

Research

Jump to: Editorial, Review

15 pages, 15405 KiB  
Article
An Operation Guide of Si-MOS Quantum Dots for Spin Qubits
by Rui-Zi Hu, Rong-Long Ma, Ming Ni, Xin Zhang, Yuan Zhou, Ke Wang, Gang Luo, Gang Cao, Zhen-Zhen Kong, Gui-Lei Wang, Hai-Ou Li and Guo-Ping Guo
Nanomaterials 2021, 11(10), 2486; https://doi.org/10.3390/nano11102486 - 24 Sep 2021
Cited by 7 | Viewed by 4172
Abstract
In the last 20 years, silicon quantum dots have received considerable attention from academic and industrial communities for research on readout, manipulation, storage, near-neighbor and long-range coupling of spin qubits. In this paper, we introduce how to realize a single spin qubit from [...] Read more.
In the last 20 years, silicon quantum dots have received considerable attention from academic and industrial communities for research on readout, manipulation, storage, near-neighbor and long-range coupling of spin qubits. In this paper, we introduce how to realize a single spin qubit from Si-MOS quantum dots. First, we introduce the structure of a typical Si-MOS quantum dot and the experimental setup. Then, we show the basic properties of the quantum dot, including charge stability diagram, orbital state, valley state, lever arm, electron temperature, tunneling rate and spin lifetime. After that, we introduce the two most commonly used methods for spin-to-charge conversion, i.e., Elzerman readout and Pauli spin blockade readout. Finally, we discuss the details of how to find the resonance frequency of spin qubits and show the result of coherent manipulation, i.e., Rabi oscillation. The above processes constitute an operation guide for helping the followers enter the field of spin qubits in Si-MOS quantum dots. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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13 pages, 7269 KiB  
Article
Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications
by Md. Hasan Raza Ansari, Udaya Mohanan Kannan and Seongjae Cho
Nanomaterials 2021, 11(7), 1773; https://doi.org/10.3390/nano11071773 - 7 Jul 2021
Cited by 18 | Viewed by 4020
Abstract
This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into [...] Read more.
This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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10 pages, 3172 KiB  
Article
Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics
by Yongliang Li, Fei Zhao, Xiaohong Cheng, Haoyan Liu, Ying Zan, Junjie Li, Qingzhu Zhang, Zhenhua Wu, Jun Luo and Wenwu Wang
Nanomaterials 2021, 11(7), 1689; https://doi.org/10.3390/nano11071689 - 28 Jun 2021
Cited by 17 | Viewed by 6240
Abstract
In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown [...] Read more.
In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O2/He plasma by optimizing its bias voltage and O2 flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current Ion, subthreshold slope (SS) and Ion/Ioff ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (Weff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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15 pages, 5552 KiB  
Article
Investigation on Ge0.8Si0.2-Selective Atomic Layer Wet-Etching of Ge for Vertical Gate-All-Around Nanodevice
by Lu Xie, Huilong Zhu, Yongkui Zhang, Xuezheng Ai, Junjie Li, Guilei Wang, Anyan Du, Zhenzhen Kong, Qi Wang, Shunshun Lu, Chen Li, Yangyang Li, Weixing Huang and Henry H. Radamson
Nanomaterials 2021, 11(6), 1408; https://doi.org/10.3390/nano11061408 - 26 May 2021
Cited by 6 | Viewed by 4125
Abstract
For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge0.8Si0.2-selective etching [...] Read more.
For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), the selective isotropic etching of Ge selective to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer etching (ALE), including Ge0.8Si0.2-selective etching of Ge and crystal-orientation selectivity of Ge oxidation, has been developed to control the etch rate and the size of the Ge nanowires. The ALE of Ge in p+-Ge0.8Si0.2/Ge stacks with 70% HNO3 as oxidizer and deionized (DI) water as oxide-removal was investigated in detail. The saturated relative etched amount per cycle (REPC) and selectivity at different HNO3 temperatures between Ge and p+-Ge0.8Si0.2 were obtained. In p+-Ge0.8Si0.2/Ge stacks with (110) sidewalls, the REPC of Ge was 3.1 nm and the saturated etching selectivity was 6.5 at HNO3 temperature of 20 °C. The etch rate and the selectivity were affected by HNO3 temperatures. As the HNO3 temperature decreased to 10 °C, the REPC of Ge was decreased to 2 nm and the selectivity remained at about 7.4. Finally, the application of ALE in the formation of Ge nanowires in vGAAFETs was demonstrated where the preliminary Id–Vds output characteristic curves of Ge vGAAFET were provided. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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14 pages, 4971 KiB  
Article
The Effect of Doping on the Digital Etching of Silicon-Selective Silicon–Germanium Using Nitric Acids
by Yangyang Li, Huilong Zhu, Zhenzhen Kong, Yongkui Zhang, Xuezheng Ai, Guilei Wang, Qi Wang, Ziyi Liu, Shunshun Lu, Lu Xie, Weixing Huang, Yongbo Liu, Chen Li, Junjie Li, Hongxiao Lin, Jiale Su, Chuanbin Zeng and Henry H. Radamson
Nanomaterials 2021, 11(5), 1209; https://doi.org/10.3390/nano11051209 - 3 May 2021
Cited by 7 | Viewed by 4279
Abstract
Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling [...] Read more.
Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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19 pages, 10592 KiB  
Article
Organotrialkoxysilane-Functionalized Prussian Blue Nanoparticles-Mediated Fluorescence Sensing of Arsenic(III)
by Prem. C. Pandey, Shubhangi Shukla and Roger J. Narayan
Nanomaterials 2021, 11(5), 1145; https://doi.org/10.3390/nano11051145 - 28 Apr 2021
Cited by 14 | Viewed by 2780
Abstract
Prussian blue nanoparticles (PBN) exhibit selective fluorescence quenching behavior with heavy metal ions; in addition, they possess characteristic oxidant properties both for liquid–liquid and liquid–solid interface catalysis. Here, we propose to study the detection and efficient removal of toxic arsenic(III) species by materializing [...] Read more.
Prussian blue nanoparticles (PBN) exhibit selective fluorescence quenching behavior with heavy metal ions; in addition, they possess characteristic oxidant properties both for liquid–liquid and liquid–solid interface catalysis. Here, we propose to study the detection and efficient removal of toxic arsenic(III) species by materializing these dual functions of PBN. A sophisticated PBN-sensitized fluorometric switching system for dosage-dependent detection of As3+ along with PBN-integrated SiO2 platforms as a column adsorbent for biphasic oxidation and elimination of As3+ have been developed. Colloidal PBN were obtained by a facile two-step process involving chemical reduction in the presence of 2-(3,4-epoxycyclohexyl)ethyl trimethoxysilane (EETMSi) and cyclohexanone as reducing agents, while heterogeneous systems were formulated via EETMSi, which triggered in situ growth of PBN inside the three-dimensional framework of silica gel and silica nanoparticles (SiO2). PBN-induced quenching of the emission signal was recorded with an As3+ concentration (0.05–1.6 ppm)-dependent fluorometric titration system, owing to the potential excitation window of PBN (at 480–500 nm), which ultimately restricts the radiative energy transfer. The detection limit for this arrangement is estimated around 0.025 ppm. Furthermore, the mesoporous and macroporous PBN-integrated SiO2 arrangements might act as stationary phase in chromatographic studies to significantly remove As3+. Besides physisorption, significant electron exchange between Fe3+/Fe2+ lattice points and As3+ ions enable complete conversion to less toxic As5+ ions with the repeated influx of mobile phase. PBN-integrated SiO2 matrices were successfully restored after segregating the target ions. This study indicates that PBN and PBN-integrated SiO2 platforms may enable straightforward and low-cost removal of arsenic from contaminated water. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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11 pages, 5733 KiB  
Article
High Performance p-i-n Photodetectors on Ge-on-Insulator Platform
by Xuewei Zhao, Guilei Wang, Hongxiao Lin, Yong Du, Xue Luo, Zhenzhen Kong, Jiale Su, Junjie Li, Wenjuan Xiong, Yuanhao Miao, Haiou Li, Guoping Guo and Henry H. Radamson
Nanomaterials 2021, 11(5), 1125; https://doi.org/10.3390/nano11051125 - 27 Apr 2021
Cited by 30 | Viewed by 4412
Abstract
In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 μm, the dark current at −1 V is 2.5 nA, which is 2.6-fold lower than [...] Read more.
In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 μm, the dark current at −1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at −1 V are as low as 1.79 mA/cm2 and 0.34 μA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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9 pages, 4335 KiB  
Article
Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods
by Qide Yao, Xueli Ma, Hanxiang Wang, Yanrong Wang, Guilei Wang, Jing Zhang, Wenkai Liu, Xiaolei Wang, Jiang Yan, Yongliang Li and Wenwu Wang
Nanomaterials 2021, 11(4), 955; https://doi.org/10.3390/nano11040955 - 9 Apr 2021
Cited by 9 | Viewed by 2379
Abstract
The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (D [...] Read more.
The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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10 pages, 3626 KiB  
Article
Epitaxial Growth of Ordered In-Plane Si and Ge Nanowires on Si (001)
by Jian-Huan Wang, Ting Wang and Jian-Jun Zhang
Nanomaterials 2021, 11(3), 788; https://doi.org/10.3390/nano11030788 - 19 Mar 2021
Viewed by 2513
Abstract
Controllable growth of wafer-scale in-plane nanowires (NWs) is a prerequisite for achieving addressable and scalable NW-based quantum devices. Here, by introducing molecular beam epitaxy on patterned Si structures, we demonstrate the wafer-scale epitaxial growth of site-controlled in-plane Si, SiGe, and Ge/Si core/shell NW [...] Read more.
Controllable growth of wafer-scale in-plane nanowires (NWs) is a prerequisite for achieving addressable and scalable NW-based quantum devices. Here, by introducing molecular beam epitaxy on patterned Si structures, we demonstrate the wafer-scale epitaxial growth of site-controlled in-plane Si, SiGe, and Ge/Si core/shell NW arrays on Si (001) substrate. The epitaxially grown Si, SiGe, and Ge/Si core/shell NW are highly homogeneous with well-defined facets. Suspended Si NWs with four {111} facets and a side width of about 25 nm are observed. Characterizations including high resolution transmission electron microscopy (HRTEM) confirm the high quality of these epitaxial NWs. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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11 pages, 2891 KiB  
Article
Flexible Carbon Nanotubes Confined Yolk-Shelled Silicon-Based Anode with Superior Conductivity for Lithium Storage
by Na Han, Jianjiang Li, Xuechen Wang, Chuanlong Zhang, Gang Liu, Xiaohua Li, Jing Qu, Zhi Peng, Xiaoyi Zhu and Lei Zhang
Nanomaterials 2021, 11(3), 699; https://doi.org/10.3390/nano11030699 - 11 Mar 2021
Cited by 21 | Viewed by 3669
Abstract
The further deployment of silicon-based anode materials is hindered by their poor rate and cycling abilities due to the inferior electrical conductivity and large volumetric changes. Herein, we report a silicon/carbon nanotube (Si/CNT) composite made of an externally grown flexible carbon nanotube (CNT) [...] Read more.
The further deployment of silicon-based anode materials is hindered by their poor rate and cycling abilities due to the inferior electrical conductivity and large volumetric changes. Herein, we report a silicon/carbon nanotube (Si/CNT) composite made of an externally grown flexible carbon nanotube (CNT) network to confine inner multiple Silicon (Si) nanoparticles (Si NPs). The in situ generated outer CNTs networks, not only accommodate the large volume changes of inside Si NPs but also to provide fast electronic/ionic diffusion pathways, resulting in a significantly improved cycling stability and rate performance. This Si/CNT composite demonstrated outstanding cycling performance, with 912.8 mAh g−1 maintained after 100 cycles at 100 mA g−1, and excellent rate ability of 650 mAh g−1 at 1 A g−1 after 1000 cycles. Furthermore, the facial and scalable preparation method created in this work will make this new Si-based anode material promising for practical application in the next generation Li-ion batteries. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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Review

Jump to: Editorial, Research

46 pages, 13917 KiB  
Review
Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon
by Yong Du, Buqing Xu, Guilei Wang, Yuanhao Miao, Ben Li, Zhenzhen Kong, Yan Dong, Wenwu Wang and Henry H. Radamson
Nanomaterials 2022, 12(5), 741; https://doi.org/10.3390/nano12050741 - 22 Feb 2022
Cited by 58 | Viewed by 6773
Abstract
Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the [...] Read more.
Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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43 pages, 12563 KiB  
Review
Review of Si-Based GeSn CVD Growth and Optoelectronic Applications
by Yuanhao Miao, Guilei Wang, Zhenzhen Kong, Buqing Xu, Xuewei Zhao, Xue Luo, Hongxiao Lin, Yan Dong, Bin Lu, Linpeng Dong, Jiuren Zhou, Jinbiao Liu and Henry H. Radamson
Nanomaterials 2021, 11(10), 2556; https://doi.org/10.3390/nano11102556 - 29 Sep 2021
Cited by 57 | Viewed by 9405
Abstract
GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular [...] Read more.
GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices. Full article
(This article belongs to the Special Issue Silicon Nanodevices)
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