Search Results (44)

Edge computing (EC) faces unique security threats due to its distributed architecture, resource-constrained devices, and diverse applications, making it vulnerable to data breaches, malware infiltration, and device compromise. The mitigation strategies against EC data security threats include encryption, secure authentication, regular updates, tamper-resistant hardware, and lightweight security protocols. Physical Unclonable Functions (PUFs) are digital fingerprints for device authentication that enhance interconnected devices’ security due to their cryptographic characteristics. PUFs produce output responses against challenge inputs based on the physical structure and intrinsic manufacturing variations of an integrated circuit (IC). These challenge-response pairs (CRPs) enable secure and reliable device authentication. Our work implements the Arbiter PUF (APUF) on Altera Cyclone IV FPGAs installed on the ALINX AX4010 board. The proposed APUF has achieved performance metrics of 49.28% uniqueness, 38.6% uniformity, and 89.19% reliability. The robustness of the proposed APUF against machine learning (ML)-based modeling attacks is tested using supervised Support Vector Machines (SVMs), logistic regression (LR), and an ensemble of gradient boosting (GB) models. These ML models were trained over more than 19K CRPs, achieving prediction accuracies of 61.1%, 63.5%, and 63%, respectively, thus cementing the resiliency of the device against modeling attacks. However, the proposed APUF exhibited its vulnerability to Multi-Layer Perceptron (MLP) and random forest (RF) modeling attacks, with 95.4% and 95.9% prediction accuracies, gaining successful authentication. APUFs are well-suited for device authentication due to their lightweight design and can produce a vast number of challenge-response pairs (CRPs), even in environments with limited resources. Our findings confirm that our approach effectively resists widely recognized attack methods to model PUFs. Full article

The use of multi-output look-up tables (LUTs) is a widely adopted approach in contemporary commercial field-programmable gate arrays (FPGAs). Larger LUT configurations (e.g., six-input LUTs) can be partitioned into smaller LUTs (e.g., two five-input LUTs, maintaining a total input count of less than six). This capability of generating a second output from a larger LUT is not only crucial for reducing logic cell count and enhancing the utilization efficiency of logic resources—thus conserving area—but also plays a key role in optimizing system-level delays and energy consumption. In this paper, we propose an efficient multi-output LUT mapping technique, incorporating several highly efficient technology mapping algorithms, which focus on optimizing the mapping from an interconnection perspective as alternatives to directly merging smaller LUTs. These algorithms include a side-fanout insertion algorithm, and a runtime multi-output cut generation algorithm. The proposed methods improve mapping efficiency and enhance performance. The benchmarking results demonstrate that the dual-output mapping algorithms achieve LUT area reductions of up to 35% and 6%, compared to the state-of-the-art ABC six-input, single-output LUT mapping technique and previous work focusing on dual-output LUT mapping techniques that optimize cut generation parameters. Moreover, FPGA system-level simulations also show that area, delay, and energy can all be optimized based on this multi-output mapping technique. Full article

Due to technological advancement, the advent of smart cities has facilitated the deployment of advanced urban management systems. This integration has been made possible through the Internet of Vehicles (IoV), a foundational technology. By connecting smart cities with vehicles, the IoV enhances the safety and efficiency of transportation. This interconnected system facilitates wireless communication among vehicles, enabling the exchange of crucial traffic information. However, this significant technological advancement also raises concerns regarding privacy for individual users. This paper presents an innovative privacy-preserving authentication scheme focusing on IoV using physical unclonable functions (PUFs). This scheme employs the k-nearest neighbor (KNN) encryption technique, which possesses a multi-multi searching property. The main objective of this scheme is to authenticate autonomous vehicles (AVs) within the IoV framework. An innovative PUF design is applied to generate random keys for our authentication scheme to enhance security. This two-layer security approach protects against various cyber-attacks, including fraudulent identities, man-in-the-middle attacks, and unauthorized access to individual user information. Due to the substantial amount of information that needs to be processed for authentication purposes, our scheme is implemented using hardware acceleration on an Nexys A7-100T FPGA board. Our analysis of privacy and security illustrates the effective accomplishment of specified design goals. Furthermore, the performance analysis reveals that our approach imposes a minimal communication and computational burden and optimally utilizes hardware resources to accomplish design objectives. The results show that the proposed authentication scheme exhibits a non-linear increase in encryption time with a growing AV ID size, starting at 5$\mathsf{\mu }$s for 100 bits and rising to 39 $\mathsf{\mu }$s for 800 bits. Also, the result demonstrates a more gradual, linear increase in the search time with a growing AV ID size, starting at less than 1 $\mathsf{\mu }$s for 100 bits and rising to less than 8 $\mathsf{\mu }$s for 800 bits. Additionally, for hardware utilization, our scheme uses only 25% from DSP slides and IO pins, 22.2% from BRAM, 5.6% from flip-flops, and 24.3% from LUTs. Full article

Neurons in the brain are interconnected through synapses. Local active memristors can both simulate the synaptic behavior of neurons and the action potentials of neurons. Currently, the hyperbolic tangent function-type memristors used for coupling neural networks do not belong to local active memristors. To take advantage of local active memristors and consider the multi-equilibrium point problem, a cosine function is introduced into the state equation, resulting in the design of an absolute value hyperbolic tangent-type double local active memristor, and it is used as a coupling synapse to replace a synaptic weight in a 3-neuron HNN. Then, basic dynamical analysis methods are used to study the effects of different memristor synapse coupling strengths and different initial conditions on the dynamics of the neural network. The research results indicate that dynamical behavior of memristor Hopfield neural network is closely related to the synaptic coupling strengths and the initial conditions, and this neural network exhibits rich dynamical behaviors, including the coexistence of chaotic and periodic attractors, super-multistability phenomena, etc. Finally, the neural network was implemented using an FPGA development board, verifying the hardware feasibility of this system. Full article

Multi-FPGA systems can form larger and more powerful computing units through high-speed interconnects between chips, and are beginning to be widely used by various computing service providers, especially in edge computing. However, the new computing architecture brings new challenges to efficient and reliable task scheduling. In this context, we propose a resource- and reliability-aware hybrid scheduling method on Multi-FPGA systems. First, a set of models is established based on the resource/time requirements, communication overhead, and state conversion process of tasks to further analyze the constraints of system scheduling. On this basis, the large task is divided into subtasks based on the data dependency matrix, and the Maintenance Multiple Sequence (MMS) algorithm is used to generate execution sequences for each subtask to the Multi-FPGA systems to fully exploit resources and ensure reliable operation. Compared with state-of-the-art scheduling methods, the proposed method can achieve an average increase in resource utilization of 7%; in terms of reliability, it achieves good execution gains, with an average task completion rate of 98.3% and a mean time to failure of 15.7 years. Full article

The dynamical behavior of a Duffing oscillator under periodic excitation is investigated using semi-analytical methods. Bifurcation trees with varying periodic excitation are constructed. The stability, saddle-node bifurcation and period-doubling bifurcation are revealed by assessing the eigenvalue of the model. From the bifurcation trees, we observed that saddle-node and period-doubling bifurcations occur when the excitation frequency and excitation amplitude vary to an appropriate value. The generation of periodic-doubling bifurcation leads to a change in the periodicity of periodic motion. The relationships among periodic-m motions are interconnected yet independent of each other. To satisfy the need of parameter selection for FPGA circuits, a dual-parameter map is calculated to study the periodic characteristics. Then, an FPGA circuit model is designed and implemented. The results show that the phase trajectory and waveform of the FPGA hardware circuit match the numerical model. Full article

When synthesizing systems for railway interlocking, it is recommended to use automated models to implement the logic of railway automation and remote control units. Finite-state machines (FSMs) can be implemented on any hardware component. When using relay technology, the functional safety of electrical interlocking is achieved by using uncontrolled (safety) relays with a high coefficient of asymmetry of failures in types 1 → 0 and 0 → 1. When using programmable components, the use of backup and diverse protection methods is required. This paper presents a flexible approach to synthesizing FSMs for railway automation and remote control units that offer both individual and route-based control. Unlike existing solutions, this proposal considers the pre-failure states of railway automation and remote control units during the finite-state machine synthesis stage. This enables the implementation of self-checking and self-diagnostic modules to manage automation units. By increasing the number of states for individual devices and considering the states of interconnected objects, the transition graphs can be expanded. This expansion allows for the synthesis of the transition graph of the control subsystem and other systems. The authors used a field-programmable gate array (FPGA) to implement a finite-state machine. In this case, the proposal is to encode the states of a finite-state machine using weight-based sum codes in the residue class ring based on a given modulus. The best coverage of errors occurring at the outputs of the logic converter in the structure of the FSM can be ensured by selecting the weighting coefficients and the value of the module. This paper presents an example of synthesizing an FPGA-based FSM using state encoding through modular weight-based sum codes. The operation of the synthesized device was modeled. It was found to operate according to the same algorithm as the real devices. When synthesizing self-checking and self-controlled train control devices, it is recommended to consider the solutions proposed in this paper. Full article

Multi-motor servo systems are widely used in industrial control. However, the single-core microprocessor architecture based on the microcontroller unit (MCU) and digital signal processor (DSP) is not well suited for high-performance multi-motor servo systems due to the inherent limitations in computing performance and serial execution of code. The bus-based distributed architecture formed by interconnecting multiple unit controllers increases system communication complexity, reduces system integration, and incurs additional hardware and software costs. Field programmable gate array (FPGA) possesses the characteristics of high real-time performance, parallel processing, and modularity. A single FPGA can integrate multiple motor servo controllers. This research uses MCU + FPGA as the core to realize high-precision multi-axis real-time control, combining the powerful performance of the MCU processor and the high-speed parallelism of FPGA. The MCU serves as the central processor and facilitates data interaction with the host computer through the controller area network (CAN). After data parsing and efficient computation, MCU communicates with the FPGA through flexible static memory controller (FSMC). A motor servo controller intellectual property (IP) core is designed and packaged for easy reuse within the FPGA. A 38-axis micro direct current (DC) motor control system is constructed to test the performance of the IP core and the heterogeneous embedded platforms. The experimental results show that the designed IP core exhibits robust functionality and scalability. The system exhibits high real-time performance and reliability. Full article

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented. Full article

Field-Programmable Gate Arrays (FPGAs) play a significant and evolving role in various industries and applications in the current technological landscape. They are widely known for their flexibility, rapid prototyping, reconfigurability, and design development features. FPGA designs are often constructed as compositions of interconnected modules that implement the various features/functionalities required in an application. This work develops a novel tool FEINT, which facilitates this module composition process and automates the design-level modifications required when introducing new modules into an existing design. The proposed methodology is architected as a “template” insertion tool that operates based on a user-provided configuration script to introduce dynamic design features as plugins at different stages of the FPGA design process to facilitate rapid prototyping, composition-based design evolution, and system customization. FEINT can be useful in applications where designers need to tailor system behavior without requiring expert FPGA programming skills or significant manual effort. For example, FEINT can help insert defensive monitoring, adversarial Trojan, and plugin-based functionality enhancement features. FEINT is scalable, future-proof, and cross-platform without a dependence on vendor-specific file formats, thus ensuring compatibility with FPGA families and tool versions and being integrable with commercial tools. To assess FEINT’s effectiveness, our tests covered the injection of various types of templates/modules into FPGA designs. For example, in the Trojan insertion context, our tests consider diverse Trojan behaviors and triggers, including key leakage and denial of service Trojans. We evaluated FEINT’s applicability to complex designs by creating an FPGA design that features a MicroBlaze soft-core processor connected to an AES-accelerator via an AXI-bus interface. FEINT can successfully and efficiently insert various templates into this design at different FPGA design stages. Full article

This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies. Full article

Multiple field programmable gate array (Multi-FPGA) systems are capable of forming larger and more powerful computing units through high-speed interconnections between chips and are beginning to be widely used by various computing service providers. However, the new computing architecture brings new challenges to the system’s task resource management. Existing resource management methods do not fully exploit resources in Multi-FPGA systems, and it is difficult to support fast resource request and release. In this regard, we propose a geometric layout-based resource management (GLRM) method for Multi-FPGA systems. First, a geometric layout-based task combination algorithm (TCA) was proposed to ensure that the final system can use the available FPGA resources more efficiently. Then, we optimised two resource management algorithms using TCA. Compared with state-of-the-art resource management methods, TCA increases resource flexibility by an average of 6% and resource utilisation by an average of 7%, and the two optimised resource management methods are effective in improving resource management performance. Full article

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements. Full article

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical–star (H–star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition. Full article

Convolutional neural networks (CNNs) have demonstrated significant superiority in modern artificial intelligence (AI) applications. To accelerate the inference process of CNNs, reconfigurable CNN accelerators that support diverse networks are widely employed for AI systems. Given the ubiquitous deployment of these AI systems, there is a growing concern regarding the security of CNN accelerators and the potential attacks they may face, including hardware Trojans. This paper proposes a hardware Trojan designed to attack a crucial component of FPGA-based CNN accelerators: the reconfigurable interconnection network. Specifically, the hardware Trojan alters the data paths during activation, resulting in incorrect connections in the arithmetic circuit and consequently causing erroneous convolutional computations. To address this issue, the paper introduces a novel detection technique based on physically unclonable functions (PUFs) to safeguard the reconfigurable interconnection network against hardware Trojan attacks. Experimental results demonstrate that by incorporating a mere 0.27% hardware overhead to the accelerator, the proposed hardware Trojan can degrade the inference accuracy of popular neural network architectures, including LeNet, AlexNet, and VGG, by a significant range of 8.93% to 86.20%. The implemented arbiter-PUF circuit on a Xilinx Zynq XC7Z100 platform successfully detects the presence and location of hardware Trojans in a reconfigurable interconnection network. This research highlights the vulnerability of reconfigurable CNN accelerators to hardware Trojan attacks and proposes a promising detection technique to mitigate potential security risks. The findings underscore the importance of addressing hardware security concerns in the design and deployment of AI systems utilizing FPGA-based CNN accelerators. Full article