Search Results (29)

This paper proposes a new behavioral model for radio-frequency power amplifiers (RF PAs) by extending the two-dimensional Polar Volterra series to fractional derivative order, using a numerical Mittag–Leffler-based formulation of fractional orthonormal generating functions. The motivation stems from the increasing need for accurate and computationally efficient models to represent nonlinearities and memory effects in wideband RF PAs, especially in energy-efficient 5G systems. The proposed method significantly reduces model complexity by lowering the number of estimated parameters while maintaining or improving modeling fidelity. To evaluate its performance, three different RF PA devices were used as test cases. The results demonstrated that the proposed approach achieved an over 81.5% reduction in the number of model parameters and improved modeling accuracy. Besides that, in a scenario with the same number of parameters, normalized mean square error (NMSE) gains of up to 8.72 dB were obtained. These findings support the method’s potential for practical use in RF PA behavioral modeling and digital predistortion applications. Full article

It may be helpful to integrate multiple aircraft communication and navigation functions into a single software-defined radio (SDR) platform. To transmit these multiple signals, the SDR would first sum the baseband version of the signals. This outgoing composite signal would be passed through a digital-to-analog converter (DAC) before being up-converted and passed through a radio frequency (RF) amplifier. To prevent non-linear distortion in the RF amplifier, it is important to know the peak voltage of the composite. While this is reasonably straightforward when a single modulation is used, it is more challenging when working with composite signals. This paper describes a machine learning solution to this problem. We demonstrate that a generalized gamma distribution (GGD) is a good fit for the distribution of the instantaneous voltage of the composite waveform. A deep neural network was trained to estimate the GGD parameters based on the parameters of the modulators. This allows the SDR to accurately estimate the peak of the composite voltage and set the gain of the DAC and RF amplifier, without having to generate or directly observe the composite signal. Full article

This paper presents a low power wideband dB-linear analog baseband (ABB) circuit for a millimeter-wave (mmW) wireless receiver in 40 nm CMOS technology. The proposed ABB system consists of a multi-stage variable gain amplifier (VGA) and a low-pass filter (LPF). The 5-stage VGA is composed of two variable gain units followed by three fixed gain units with DC offset cancellation (DCOC). The first variable gain unit with a self-compensated transistor pair and compact active inductor load is designed for dB-linear functionality and bandwidth extension, respectively. Moreover, a proposed error compensation method is applied to the second cascaded variable gain unit for further dB-linear gain error correction. A 4th-order Butterworth transconductance-capacitance (Gm-C) LPF with flipped source follower (FSF) as an input transconductance stage for linearity enhancement is designed after the VGA stage. The prototype chip is implemented, and measurement results show a dB-linear gain range from −18 to 26 dB with less than 0.5 dB-linear gain error with a bandwidth of 4 GHz. The VGA and LPF consume 8.3 mW and 3 mW, respectively, under a 1 V power supply, while the entire ABB occupies an area of 0.94 mm² with an active core area of only 0.045 mm². Full article

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode. Full article

For the existing outphasing architectures of an all-digital transmitter (ADTx), the required sampling rate of the signal is too high, which increases the difficulty of digital radio frequency pulse width modulation (RF-PWM) processing. In this paper, we present an outphasing architecture based on the parallel RF-PWM method for an ADTx. Through polyphase interpolation, two baseband outphasing signals are divided into multiple low-rate signals to process simultaneously. The parallel outphasing signals are modulated and encoded to obtain 1-bit parallel signals, which are, respectively, transmitted to multigigabit transceivers (MGTs) to generate two two-level high-speed pulses with different phases. Finally, a three-level high-speed pulse is synthesized and amplified through the switching power amplifier. Through this parallel scheme, the sampling rate of digital RF-PWM signal processing is effectively reduced. Moreover, to explore a pulse encoding method, the outphasing architecture is combined with a zero-crossing comparison through an angle calculation and quadrant judgment, which simplifies the modulation and encoding process. In addition, the impact of the sub-filter order and the number of parallel paths on system performance is analyzed. The simulation results show that for a 16QAM signal with a baseband bandwidth of 20 MHz and a carrier frequency of 200 MHz, the adjacent channel power ratio (ACPR) is below −45 dBc and the error vector magnitude (EVM) is below 1% in the proposed scheme. Full article

D-band (110–170 GHz) has been regarded as a potential candidate for the future 6G wireless network because of its large available bandwidth. At present, the lack of electrical amplifiers operating in the high frequency band and the strong nonlinear effect, i.e., the D-band, are still important problems. Therefore, effective methods to mitigate the nonlinear issue resulting from the ROF link are indispensable, among of which machine learning is considered the most effective paradigm to model the nonlinear behavior due to its nonlinear active function and structure. In order to reduce the computation amount and burden, a novel deep learning neural network equalizer connected with typical mathematical frequency offset estimation (FOE) and carrier phase recovery (CPR) algorithms is proposed. We implement D-band 45 Gbaud PAM-4 and 20 Gbaud PAM-8 ROF transmission simulations, and the simulation results show that the real value neural network (RVNN) equalizer connected with the Viterbi-Viterbi algorithm exhibits better compensation ability for nonlinear impairment, especially when dealing with serious inter-symbol interference and nonlinear effects. In our experiment, we employ coherent detection to further improve the receiver sensitivity, so a complex baseband signal after down conversion at the receiver is inherently produced. In this scenario, the complex value neural network (CVNN) and RVNN equalizer connected with the Viterbi-Viterbi algorithm have better BER performance with an error rate lower than the HD-FEC threshold of 3.8 × 10⁻³. Full article

In signal communication based on a non-cooperative communication system, the receiver is an unlicensed third-party communication terminal, and the modulation parameters of the transmitter signal cannot be predicted in advance. After the RF signal passes through the RF band-pass filter, low noise amplifier, and image rejection filter, the intermediate frequency signal is obtained by down-conversion, and then the IQ signal is obtained in the baseband by using the intermediate frequency band-pass filter and down-conversion. In this process, noise and signal frequency offset are inevitably introduced. As the basis of subsequent analysis and interpretation, modulation recognition has important research value in this environment. The introduction of deep learning also brings new feature mining tools. Based on this, this paper proposes a signal modulation recognition method based on multi-feature fusion and constructs a deep learning network with a double-branch structure to extract the features of IQ signal and multi-channel constellation, respectively. It is found that through the complementary characteristics of different forms of signals, a more complete signal feature representation can be constructed. At the same time, it can better alleviate the influence of noise and frequency offset on recognition performance, and effectively improve the classification accuracy of modulation recognition. Full article

Long-range E-band communication with fiber-equivalent speed is emerging extensively as a critical technology in the next-generation communication. This paper firstly reviews the relevant progress in recent research. A brief survey is presented on high-speed, long-range E-band communication systems and their relevant techniques that are essential to the link design, including antenna, power amplifier (PA), channel, and digital baseband processing. In the second part, we review our recent field trial of a long-range air-to-ground E-band link, which maintains steady transmission from a slow-moving helium balloon to the ground station with a vertical dimension of 20 km. The improvement directions and future research topics are then discussed. Full article

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, requiring less area. The transimpedance amplifier (TIA) and low-noise transconductance amplifier (LNTA) share the bias current from a single supply to reduce power consumption. It employs both an active-inductor (AI) and a $1/f$ noise-cancellation technique to improve the NF and RF bandwidth performance. A passive mixer is utilized for RF to BB conversion, which does not require any DC power and voltage headroom. Both CRR1 and CRR2 are fabricated in TSMC $130 \mathrm{n}\mathrm{m}$ CMOS technology on a single die and packaged using a QFN48. CRR1 occupies an active area of 0.54 ${\mathrm{mm}}^2$. From 1 to $1.7$$\mathrm{G}$$\mathrm{Hz}$, it achieves a conversion gain of $41.5$ $\mathrm{d}$$\mathrm{B}$, a double-sideband (DSB) NF of $6.5$ $\mathrm{d}$$\mathrm{B}$, ${\mathrm{S}}_{11}<$$-10$ $\mathrm{d}$$\mathrm{B}$, and an IIP3 of $-28.2$ $\mathrm{d}$$\mathrm{Bm}$, while the local-oscillator (LO) frequency is at $1.3$ $\mathrm{G}$$\mathrm{Hz}$. CRR2 occupies an active area of 0.025 ${\mathrm{mm}}^2$. From 0.2 to 1 $\mathrm{G}$$\mathrm{Hz}$, it achieves an average conversion gain of 37 $\mathrm{d}$$\mathrm{B}$, an average DSB NF of 8 $\mathrm{d}$$\mathrm{B}$, and an IIP3 of $-21.5$ $\mathrm{d}$$\mathrm{Bm}$ while the LO frequency is at $0.7$ $\mathrm{G}$$\mathrm{Hz}$. Both CRR1 and CRR2 consume $1.66$ $\mathrm{m}\mathrm{A}$ from a $1.2$ $\mathrm{V}$ supply voltage. Full article

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer’s LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, −35.2 dBm input-referred 1 dB compression power, and 4.8–7.1 dB noise figure across 22.5–26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0–1.5 dB to 0.02–0.19 dB, and from 10.8–23.8 to 1.1–3.2 degrees, respectively. Full article

A good approximation to power amplifier (PA) behavioral modeling requires precise baseband models to mitigate nonlinearities. Since digital predistortion (DPD) is used to provide the PA linearization, a framework is necessary to validate the modeling figures of merit support under signal conditioning and transmission restrictions. A field-programmable gate array (FPGA)-based testbed is developed to measure the wide-band PA behavior using a single-carrier 64-quadrature amplitude modulation (QAM) multiplexed by orthogonal frequency-division multiplexing (OFDM) based on long-term evolution (LTE) as a stimulus, with different bandwidths signals. In the search to provide a heuristic target approach modeling, this paper introduces a feature extraction concept to find an appropriate complexity solution considering the high sparse data issue in amplitude to amplitude (AM-AM) and amplitude to phase AM-PM models extraction, whose penalties are associated with overfitting and hardware complexity in resulting functions. Thus, experimental results highlight the model performance for a high sparse data regime and are compared with a regression tree (RT), random forest (RF), and cubic-spline (CS) model accuracy capabilities for the signal conditioning to show a reliable validation, low-complexity, according to the peak-to-average power ratio (PAPR), complementary cumulative distribution function (CCDF), coefficients extraction, normalized mean square error (NMSE), and execution time figures of merit. The presented models provide a comparison with original data that aid to compare the dimension and robustness for each surrogate model where (i) machine learning (ML)-based and (ii) CS interpolate-based where high sparse data are present, NMSE between the CS interpolated based are also compared to demonstrate the efficacy in the prediction methods with lower convergence times and complexities. Full article

This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130 $\mathrm{n}$$\mathrm{m}$ CMOS technology and occupies an active area of 0.025 ${\mathrm{mm}}^2$. It achieves a wideband input matching of less than $-10$ $\mathrm{d}$$\mathrm{B}$ from $0.8$ $\mathrm{G}$$\mathrm{Hz}$ to $3.4$ $\mathrm{G}$$\mathrm{Hz}$. A conversion-gain of $39.5$ $\mathrm{d}$$\mathrm{B}$, IIP3 of $-28$ $\mathrm{d}$$\mathrm{Bm}$ and a double-sideband (DSB) NF of $5.6$ $\mathrm{d}$$\mathrm{B}$ is simulated at a local-oscillator (LO) frequency of $2.4$ $\mathrm{G}$$\mathrm{Hz}$ and an intermediate frequency (IF) of 10 $\mathrm{M}$$\mathrm{Hz}$, while consuming $1.92$ mA from a $1.2$ $\mathrm{V}$ supply. Full article

This paper presents a 60 GHz CMOS I/Q receiver for the high-speed wireless communication system. It consists of a low noise amplifier, single-to-differential (S2D) amplifier, passive mixer, buffer amplifier with passive I/Q generator, and wideband baseband amplifier (BBA) stage. The measured conversion gain of 51 dB is achieved. The baseband bandwidth of 300 MHz is achieved from 57 GHz to 60 GHz. The 90° tandem coupler was implemented for I/Q signal generation, which has a phase error of <7° and an amplitude imbalance of <2 dB from 55 to 62 GHz. The Marchand balun is used to convert the I/Q signal to the differential, which has a phase error of <4°. A 60 GHz CMOS I/Q receiver is designed and fabricated, using a commercial 40 nm CMOS bulk process. The size of the receiver is 2.02 × 1.45 mm², including the pads. The circuit is operated from a 0.9 V supply. The power consumption is 172 mW at maximum gain mode. Full article

With the introduction of Internet of Things (IoT) technology in several sectors, wireless, reliable, and energy-saving communication in distributed sensor networks are more important than ever. Thereby, wake-up technologies are becoming increasingly important as they significantly contribute to reducing the energy consumption of wireless sensor nodes. In an indoor environment, the use of wireless sensors, in general, is more challenging due to signal fading and reflections and needs, therefore, to be critically investigated. This paper discusses the performance analysis of wake-up receiver (WuRx) architectures based on two low frequency (LF) amplifier approaches with regard to sensitivity, power consumption, and package error rate (PER). Factors that affect systems were compared and analyzed by analytical modeling, simulation results, and experimental studies with both architectures. The developed WuRx operates in the 868 MHz band using on-off-keying (OOK) signals while supporting address detection to wake up only the targeted network node. By using an indoor setup, the signal strength and PER of received signal strength indicator (RSSI) in different rooms and distances were determined to build a wireless sensor network. The results show a wake-up packets (WuPts) detection probability of about 90% for an interior distance of up to 34 m. Full article

A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration technique for fifth generation (5G) wireless communication applications. The RF transmitter comprises a baseband amplifier, quadrature up-conversion mixer, power amplifier driver, and quadrature LO generator. The I/Q amplitude mismatch is calibrated by tuning the gate biases of the switching stage FETs of the mixer, the I/Q phase mismatch is calibrated by tuning the varactor capacitances at the LC load of LO buffer, and the dc offset is cancelled by tuning the body voltages of the differential-pair FETs at the baseband amplifier. The proposed technique provides precise calibration accuracy by employing mV-resolution tuning voltage generation via 6-bit voltage digital-to-analog converters. It also covers wide calibration range while minimizing the impact on the circuit’s bias point and dissipated current during calibration. Implemented in a 65 nm CMOS process, the RF transmitter integrated circuit shows output-referred 1 dB compression power of +6.5 dBm, saturated output power of +12.6 dBm, and an operating band of 27.5–29.3 GHz while demonstrating satisfactory performances of −55.9 dBc of IRR and −36.8 dBc of LOFT. Full article