Search Results (56)

This work presents a high-common-mode-rejection-ratio (CMRR) and high-gain FinFET-based bio-potential amplifier with a novel CMRR reduction technique. In this paper, a feedback buffer is used alongside a capacitively coupled chopper-stabilized circuit to reduce the common-mode signal gain, thus boosting the overall CMRR of the circuit. The conventional pseudoresistor in the feedback circuit is replaced with a tunable parallel-cell configuration of pseudoresistors to achieve high linearity. A chopper spike filter is used to mitigate spikes generated by switching activity. The mid-band gain of the chopper-stabilized amplifier is 42.6 dB, with a bandwidth in the range of 6.96 Hz to 621 Hz. The noise efficiency factor (NEF) of the chopper-stabilized amplifier is 6.1, and its power dissipation is 0.92 µW. The linearity of the parallel pseudoresistor cell is tested for different tuning voltages (V_tune) and various numbers of parallel pseudoresistor cells. The simulation results also demonstrate the pseudoresistor cell performance for different process corners and temperature changes. The low cut-off frequency is adjusted by varying the parameters of the parallel pseudoresistor cell. The CMRR of the chopper-stabilized amplifier, with and without the feedback buffer, is 106.9 dB and 100.3 dB, respectively. The feedback buffer also reduces the low cut-off frequency, demonstrating its multi-utility. The proposed circuit is compatible with bio-signal acquisition and processing. Additionally, a machine learning-based arrhythmia diagnosis model is presented using a convolutional neural network (CNN) + Long Short-Term Memory (LSTM) algorithm. For arrhythmia diagnosis using the CNN+LSTM algorithm, an accuracy of 99.12% and a mean square error (MSE) of 0.0273 were achieved. Full article

This paper proposes a high-reliability power conversion system optimized for Urban Air Mobility (UAM) applications, which utilizes silicon carbide (SiC) chopper modules within a hybrid fuel cell and battery structure. The system features a redundant power configuration that employs both a main and an auxiliary battery to ensure continuous and stable power supply, even under emergency or fault conditions. By integrating SiC-based power converters, the proposed system achieves high efficiency, low switching losses, and enhanced thermal performance, which are crucial for the space- and weight-constrained environment of UAM platforms. Furthermore, a robust control strategy is implemented to enable smooth transitions between multiple power sources, maintaining operational stability and safety. System-level simulations were conducted using PowerSIM to validate the performance and reliability of the proposed architecture. The results demonstrate its effectiveness, making it a strong candidate for future UAM power systems requiring lightweight, efficient, and fault-tolerant power solutions. Full article

In this paper, a high-voltage chopper and ping-pong auto-zeroing operational amplifier was designed for industrial and automotive applications. Based on chopper stabilization, the proposed circuit introduces a novel chopper switch control signal that varies with the input common-mode voltage. This scheme effectively suppresses the reference offset caused by the chopper switches and prevents transistor breakdown under high-voltage conditions. Additionally, the ping-pong auto-zero structure was optimized by employing a six-channel parallel first-stage amplifier, which further reduced the charge injection and ripple introduced by the chopper switches. The amplifier was implemented using an SMIC (Semiconductor Manufacturing International Corporation) 180 nm 1P5M BCD (Bipolar-CMOS-DMOS) process with a chip area of 4.211 mm². The post-layout simulation results show that, under a 55 V supply, the amplifier achieves an input-referred noise Power Spectral Density (PSD) of 6.2 $\mathrm{nV}/\sqrt{\mathrm{Hz}}$ and an input offset voltage of 32 $\mu \mathrm{V}$, while the output voltage swings from 0.2 V to 53.4 V with a unity gain bandwidth of 3.2 MHz, which meets the requirements for high-voltage, high-resolution signal processing. Full article

Embedded differential temperature sensors can be utilized to monitor the power consumption of circuits, taking advantage of the inherent on-chip electrothermal coupling. Potential applications range from hardware security to linearity, gain/bandwidth calibration, defect-oriented testing, and compensation for circuit aging effects. This paper introduces the use of on-chip differential temperature sensors as part of a wireless Internet of Things system. A new low-power differential temperature sensor circuit with chopped cascode transistors and switched-capacitor integration is described. This design approach leverages chopper stabilization in combination with a switched-capacitor integrator that acts as a low-pass filter such that the circuit provides offset and low-frequency noise mitigation. Simulation results of the proposed differential temperature sensor in a 65 nm complementary metal-oxide-semiconductor (CMOS) process show a sensitivity of $33.18\mathrm{V}{/}^{°}\mathrm{C}$ within a linear range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$ and an integrated output noise of $0.862{\mathrm{mV}}_{\mathrm{rms}}$ (from 1 to 441.7 Hz) with an overall power consumption of $0.187\mathrm{mW}$. Considering a figure of merit that involves sensitivity, linear range, noise, and power, the new temperature sensor topology demonstrates a significant improvement compared to state-of-the-art differential temperature sensors for on-chip monitoring of power dissipation. Full article

This paper proposes a high-precision low-power interface circuit for two-dimensional (2D) integrated magnetic switches that can detect 2D magnetic fields and output 5 V CMOS digital signals. The interface circuit combines chopper stabilization and output offset storage technology to effectively suppress the offset of the entire signal chain and significantly improve detection accuracy. Additionally, an architecture-level signal processing algorithm is proposed, which not only realizes full polarity detection of the magnetic field at a low cost but also realizes switch detection of multi-dimensional magnetic fields in the interface circuit without additional processing. Furthermore, the circuit provides flexible adjustment of both switch trip thresholds and hysteresis windows through 4-bit off-chip trimming codes, which greatly enhances the universality of the interface circuit. This chip is implemented using 180 nm BCD technology with a chip area of 1.18 ${\mathrm{mm}}^2$. The measurement results show that the interface circuit can simultaneously process 2D input signals with a resolution of less than 85 μV. In addition, through a 4-bit trim code, the interface circuit can adjust the switch trip threshold in the range of 0–13.52 mV and the hysteresis interval in the range of 0–7.32 mV. The average current consumption of the chip is 6.757 μA. Full article

In order to reduce the economic costs, enhance the efficiency, and improve the structural stability of microgrids, this paper proposes a novel AC/DC hybrid microgrid structure. This structure, based on Silicon Controlled Converters (SCCs) and Polarity Reversal Switches (PRSs), enables bidirectional power flow and provides a low-cost and straightforward control solution. This paper elaborates on the overall control strategy of the microgrid under different states of the PRS and introduces the control logic of the Current Reversible Chopper (CRC) circuit. For typical daily scenarios across the four seasons, where wind and photovoltaic (PV) power generation outputs and load demands vary, this study combines sampled data to investigate the coordinated configuration scheme of wind energy, PV energy, and energy storage within the microgrid, and analyzes the state changes in the PRS. Furthermore, this paper conducts simulation analysis of the microgrid under different states of the PRS and during the switching process of the PRS, verifying the feasibility of the proposed new structure. Finally, this paper compares the proposed structure with traditional microgrid structures in terms of economics, system efficiency, and structural stability, and analyzes the impact of this structure on the frequency, inertia, and multi-energy interaction of the system. Full article

This paper presents a low-power and area-efficient chopper-stabilized low noise amplifier (CS-LNA) for in-pixel neural recording systems. The proposed CS-LNA can be used in a multi-channel architecture, in which the chopper mixers of the LNA are exploited to provide the time division multiplexing (TDM) of several channels, while reducing the flicker noise and rejecting the Electrode DC Offset (EDO). A detailed noise analysis including the effect of the chopper stabilization on flicker noise, and a design flow to optimize the trade-off between input-referred noise and silicon area are presented, and utilized to design the LNA. The adopted approach to reject the EDO allows to tolerate an input offset of ±50 mV, without appreciably affecting the CS-LNA performance, and does not require an additional DC Servo Loop (DSL). The proposed CS-LNA has been fabricated in a 0.13 μm CMOS process with an area of 0.0268 mm², consuming about 2 μA from a 0.8 V supply voltage. It achieves an integral noise of 4.19 μVrms (2.58 μVrms) from 1 to 7.5 kHz (from 300 to 7.5 kHz) and results in a noise efficiency factor (NEF) of 2.63 (1.62). Besides achieving a maximum gain of 38.67 dB with a tuning range of about 12 dB, the neural amplifier exhibits a CMRR of 67 dB. A comparison with the recent literature dealing with in-pixel amplifiers shows state-of-the-art performance. Full article

This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, automotive electronics, nuclear industry, and in other fields where the ability of electronic devices to withstand high-temperature environments is strongly required. By utilizing a SC (Switched Capacitor) notch filter, the op amp achieves low input offset in a power-efficient manner. The circuit features a multi-path nested Miller compensation structure, consisting of a low-speed channel and a high-speed channel, which switch according to the input signal frequency. The input-stage operational amplifier is a fully differential, rail-to-rail design, utilizing tail current control to reduce the impact of common-mode voltage on the transconductance of the input stage. The two-stage operational amplifier uses both cascode and Miller compensation, minimizing the influence of the feedforward signal path and improving the amplifier’s response speed. The prototype op amp is fabricated in a 0.15 µm SOI process and draws 0.3 mA from a 5 V supply. The circuit occupies a chip area of 0.76 mm². The measured open-loop gain exceeds 140 dB, with a 3 dB bandwidth greater than 100 kHz. The amplifier demonstrates stable performance across a wide temperature range from −40 °C to 250 °C, and exhibits an excellent input offset of approximately 20 µV at room temperature and an offset voltage temperature coefficient of 0.7 μV/°C in the full temperature range. Full article

Over the past few decades, wind energy has expanded to become a widespread, clean, and sustainable energy source. However, integrating offshore wind energy with the onshore AC grids presents many stability and control challenges that hinder the reliability and resilience of AC grids, particularly during faults. To address this issue, current grid codes require offshore wind farms (OWFs) to remain connected during and after faults. This requirement is challenging because, depending on the fault location and power flow direction, DC link over- or under-voltage can occur, potentially leading to the shutdown of converter stations. Therefore, this necessitates the proper understanding of key technical concepts associated with the integration of OWFs. To help fill the gap, this article performs an in-depth investigation of existing alternating current fault ride through (ACFRT) techniques of modular multilevel converter-based high-voltage direct current (MMC-HVDC) for OWFs. These techniques include the use of AC/DC choppers, flywheel energy storage devices (FESDs), power reduction strategies for OWFs, and energy optimization of the MMC. This article covers both scenarios of onshore and offshore AC faults. Given the importance of wind turbines (WTs) in transforming wind energy into mechanical energy, this article also presents an overview of four WT topologies. In addition, this article explores the advanced converter topologies employed in HVDC systems to transform three-phase AC voltages to DC voltages and vice versa at each terminal of the DC link. Finally, this article explores the key stability and control concepts, such as small signal stability and large disturbance stability, followed by future research trends in the development of converter topologies for HVDC transmission such as hybrid HVDC systems, which combine current source converters (CSCs) and voltage source converters (VSCs) and diode rectifier-based HVDC (DR-HVDC) systems. Full article

This study aimed to determine the optimal growth stage and additives for producing high quality millet silage through two experiments. Experiment 1: Whole-plant millet from the same field and under uniform management was harvested at the heading, sizing, milking, dough, and full-maturity stages. Then, it was chopped into 2–3 cm segments, vacuum-sealed in plastic bags without any further treatment, stored at 20 °C, and opened after 60 days. The results indicated that the dough stage had the highest water-soluble carbohydrate (WSC) and crude protein (CP) contents. The lactic acid (LA) and acetic acid (AA) contents during the dough and maturity stages were significantly higher than other stages, with the lowest pH observed during the dough stage. Experiment 2: The whole-plant millet was harvested at the dough stage. It was then chopped into 2–3 cm segments using a forage chopper, mixed thoroughly, and subjected to different treatments—inoculation with 10⁶ CFU/g FM of Lactiplantibacillus plantarum (LP), adding of 1% FM sucrose (S), and a combination of Lactiplantibacillus plantarum and sucrose (MIX)—with a control group (CK) receiving an equivalent amount of water. The MIX treatment significantly enhanced the WSC content compared to other treatments (p < 0.05), and both the LP and MIX treatments showed superior LA and AA contents and lactic acid bacteria counts. These additives significantly altered the bacterial community, shifting dominance from Proteobacteria in the CK and raw materials to Firmicutes. Klebsiella dominated the CK group but was significantly reduced in the additive treatments, where Lentilactobacillus became the dominant genus. Therefore, we recommend harvesting millet at the dough stage and adding a mixture of Lactiplantibacillus plantarum and sugar to improve fermentation quality and aerobic stability. Full article

In order to enhance the transient stability of offshore wind turbines (OWTs) in marine energy systems, the grid codes stipulate that OWTs should possess the low-voltage ride-through (LVRT) ability of being grid-tied and injecting reactive current during grid fault. However, the grid-side converter (GSC) of OWTs may lose stability under weak grid or severe fault conditions due to inaccurate current references. To address this issue, a novel transient current control method is proposed to improve the transient stability of permanent-magnet-synchronous-generator (PMSG)-based OWTs. The feature of DC-link overvoltage is investigated and is alleviated by utilizing the GSC’s overcurrent capacity and chopper. Additionally, the equivalent circuit of the PMSG-based OWT connected to the onshore grid is derived based on Thevenin’s theorem. The feasible current region (FCR) is then determined, taking into account the GSC capacity, pre-fault power ability, LVRT requirement, and synchronization stability. Furthermore, a grid-impedance-based transient current control method is designed to enhance the fault ride-through performance and mitigate power oscillation of the OWT under various transient grid impedance and fault conditions. Finally, a simulation model is conducted using PSCAD v4.6.3 software to validate the effectiveness of the proposed method. Full article

A time-differential (TD) Brillouin optical correlation domain analysis (BOCDA) sensor system was applied to measure the Brillouin gain spectrum of a 1 km long sensing optical fiber. The optical delay line used in all BOCDA measurement systems was eliminated in the TD-BOCDA system by using a bit-delayed modulation relationship between the probe and pump lightwaves. These lightwaves were phase modulated using 2¹⁶-1 pseudo-random binary sequence codes at 5 Gbps. A 2 cm dispersion-shifted fiber placed at the end of the 1 km optical fiber was distinctly identified by the Brillouin frequency extracted from the Brillouin gain spectrum measurement. To investigate the measurement stability of the TD-BOCDA system, experiments were conducted under two different pumping conditions. A semiconductor optical amplifier (SOA) and an intensity modulator (MOD) were compared for the pump chopper used in the TD-BOCDA system to detect the extinction ratio of the pump and the resulting noise in the Brillouin gain measurement. The stability of the Brillouin frequency measurement from the Brillouin gain spectrum in the TD-BOCDA system was investigated by increasing the average value of the measurement using either the SOA or MOD. The repeated-measurement deviation of the system with the SOA was only half of the deviation observed in the system with the MOD. The performance of TD-BOCDA is equivalent to or better than that of conventional BOCDAs in terms of measurement reliability. Moreover, TD-BOCDA is free from the drawbacks of traditional BOCDA, which uses time-delayed fibers and varies the bit rates. Full article

An optimization technique, the Kepler optimizer (KO), is presented to enable permanent magnet synchronous wind generators (PMSWG) to run safely under faults and to accomplish the goal of low-carbon efficient power delivery and sustainable development. Utility companies are struggling, which is preventing the increase in wind penetration, in spite of the grid incorporation of PMSWG. One of these undisputed concerns is the grid-side voltage dip (VD) and swell (VS) at the PCC. Converters and DCL capacitors are particularly vulnerable to PCC nonstandard voltages because of an imbalance in the DCL input–output powers. Because of this, it is essential to provide WF-GCs to support grid operations, and developing techniques to realize FRTCs has become a crucial GC need. Installing an industrial braking chopper (BC) across the DCL is the suggested technique, due to its effectiveness and low price. In addition, a new KO-based control system for BC is used to enhance its effectiveness. Four situations were examined to assess and analyze the proposed control system regarding the transient response of the system. These situations exposed the investigated system to an irregular grid condition: without BC, with BC controlled by a hysteresis controller, and with BC controlled by KO-based PI (proposed) at (a) 100% VD, (b) 70% VD, (c) 30% VD, and (d) 20% VS. To verify the advantages and efficacy of the suggested control systems in the examined circumstances, MATLAB/SIMULINK was utilized. The simulation findings confirmed the feasibility of the suggested system as a whole and the control structures in suppression of all parameter transient changes, while also achieving FRTC. Furthermore, maintaining a steady DCL voltage serves as an advantage that would lengthen the electrical converters’ lifetime and shorten the time that the unit would be turned off if it happens to fail. Full article

Voltage standards are widely used to transfer volts from Josephson voltage standards (JVSs) at national metrology institutes (NMIs) into calibration labs to maintain the volts and to transfer them to test equipment at production lines. Therefore, commercial voltage standards based on Zener diodes are used. Analog Devices Inc. (San Jose, CA, USA), namely, Eric Modica, introduced the ADR1000KHZ, a successor to the legendary LTZ1000, at the Metrology Meeting 2021. The first production samples were already available prior to this event. In this article, this new temperature-stabilized Zener diode is compared to several others as per datasheet specifications. Motivated by the superior parameters, a 10 V transfer standard prototype for laboratory use with commercial off-the-shelf components such as resistor networks and chopper amplifiers was built. How much effort it takes to reach the given parameters was investigated. This paper describes how the reference was set up to operate it at its zero-temperature coefficient (z.t.c.) temperature and to lower the requirements for the oven stability. Furthermore, it is shown how the overall temperature coefficient (t.c.) of the circuit was reduced. For the buffered Zener voltage, a t.c. of almost zero, and with amplification to 10 V, a t.c. of <0.01 µV/V/K was achieved in a temperature span of 15 to 31 °C. For the buffered Zener voltage, a noise of ~584 nVp-p and for the 10 V output, ~805 nVp-p were obtained. Finally, 850 days of drift data were taken by comparing the transfer standard prototype to two Fluke 7000 voltage standards according to the method described in NBS Technical Note 430. The drift specification was, however, not met. Full article

Voltage source converter (VSC)-based multi-terminal direct current (MTDC) transmission technology has been a research focus, and the low-voltage ride-through (LVRT) and recovery in receiving-end systems is one of the major problems to consider. A coordinated control strategy for a VSC-MTDC system is proposed to improve the frequency and voltage dynamics in the receiving-end system during the LVRT and recovery processes. A battery energy storage system (BESS) plays a significant role in providing frequency and voltage support with its flexible power control capability. During the LVRT process, the BESS can provide reactive current injection and active current absorption to improve system stability in the AC side, and during the recovery process, an adaptive current limitation method is proposed for the BESS converter to dynamically adjust the active and reactive power outputs according to the frequency and voltage deviation severity. Meanwhile, the coordination of the sending-end systems and DC chopper can reduce the power output to avoid DC overvoltage during LVRT, and it can also provide frequency support to the receiving-end system with the DC voltage transmitting frequency information during the recovery process. A simulation was carried out on the MATLAB/Simulink platform, and a three-terminal VSC-MTDC system was used to validate the effectiveness of the proposed strategy. Full article