Search Results (14)

Silicon carbide (SiC) half-bridge power modules are widely utilized in new energy power generation, electric vehicles, and industrial power supplies. To address the research gap in collaborative validation between electro-thermal coupling models and process reliability, this paper proposes a closed-loop methodology of “design-simulation-process-validation”. This approach integrates in-depth electro-thermal simulation (LTspice XVII/COMSOL Multiphysics 6.3) with micro/nano-packaging processes (sintering/bonding). Firstly, a multifunctional double-pulse test board was designed for the dynamic characterization of SiC devices. LTspice simulations revealed the switching characteristics under an 800 V operating condition. Subsequently, a thermal simulation model was constructed in COMSOL to quantify the module junction temperature gradient (25 °C → 80 °C). Key process parameters affecting reliability were then quantified, including conductive adhesive sintering (S820-F680, 39.3 W/m·K), high-temperature baking at 175 °C, and aluminum wire bonding (15 mil wire diameter and 500 mW ultrasonic power/500 g bonding force). Finally, a double-pulse dynamic test platform was established to capture switching transient characteristics. Experimental results demonstrated the following: (1) The packaged module successfully passed the 800 V high-voltage validation. Measured drain current (4.62 A) exhibited an error of <0.65% compared to the simulated value (4.65 A). (2) The simulated junction temperature (80 °C) was significantly below the safety threshold (175 °C). (3) Microscopic examination using a Leica IVesta 3 microscope (55× magnification) confirmed the absence of voids at the sintering and bonding interfaces. (4) Frequency-dependent dynamic characterization revealed a 6 nH parasitic inductance via Ansys Q3D 2025 R1 simulation, with experimental validation at 8.3 nH through double-pulse testing. Thermal evaluations up to 200 kHz indicated 109 °C peak temperature (below 175 °C datasheet limit) and low switching losses. This work provides a critical process benchmark for the micro/nano-manufacturing of high-density SiC modules. Full article

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. Full article

Due to the influence of parasitic internal parameters and junction capacitance, the silicon carbide (SiC) power devices are frequently marred by significant overshoots in current and voltage, as well as high-frequency oscillations during the switching process. These phenomena can severely compromise the reliability of SiC-based power electronic converters during operation. This study delves into the switching transient of the SiC MOSFET with the goal of establishing a quantitative correlation between the gate driving current and the overshoot in both the drain-source voltage and the drain current. In light of these findings, the innovative active gate drive (AGD) circuit, which features an adjustable gate current, is introduced. Throughout the switching process, the AGD circuit employs a dynamic monitoring and feedback mechanism that is responsive to the gate voltage and rate of change in the drain-source voltage and drain current of the SiC MOSFET. This adjustment enables gate driving current to be actively modified, thereby effectively mitigating the occurrence of overshoots and oscillations. To empirically validate the efficacy of the proposed AGD circuit in curbing voltage and current overshoots and oscillations, a double-pulse experimental setup was meticulously constructed and tested. Full article

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (V_GS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (V_GS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length L_eff = 0.25 µm and a SiO₂ gate-oxide thickness T_ox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage V_DDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients. Full article

In this paper, a single-event transient model based on the effective space charge for MOSFETs is proposed. The physical process of deposited and moving charges is analyzed in detail. The influence of deposited charges on the electric field in the depletion region is investigated. The electric field decreases in a short time period due to the neutralization of the space charge. After that, the electric field increases first and then decreases when the deposited charge is moved out. The movement of the deposited charge in the body mainly occurs through ambipolar diffusion because of its high-density electrons and holes. The derivation of the variation in electric field in the depletion region is modeled in the physical process according to the analysis. In combination with the ambipolar diffusion model of excessive charge in the body, a physics-based model is built to describe the current pulse in the drain terminal. The proposed model takes into account the influence of multiple factors, like linear-energy transfer (LET), drain bias, and the doping concentration of the well. The model results are validated with the simulation results from TCAD. Through calculation, the root-mean-square error (RMSE) between the simulation and model is less than 3.7 × 10⁻⁴, which means that the model matches well with the TCAD results. Moreover, a CMOS inverter is simulated using TCAD and SPICE to validate the applicability of the proposed model in a circuit-level simulation. The proposed model captures the variation in net voltage in the inverter. The simulation result obviously shows the current plateau effect, while the relative error of the pulse width is 23.5%, much better than that in the classic model. In comparison with the classic model, the proposed model provides an RMSE of 7.59 × 10⁻⁵ for the output current curve and an RMSE of 0.158 for the output voltage curve, which are significantly better than those of the classic model. In the meantime, the proposed model does not produce extra simulation time compared with the classic double exponential model. So, the model has potential for application to flow estimation of the soft error rate (SER) at the circuit level to improve the accuracy of the results. Full article

Our investigation focused on assessing the influence of the metamorphic buffer in metamorphic high-electron-mobility transistors (MHEMT) that were grown on GaAs substrates. While an MHEMT exhibited elevated off-state current levels, its direct current (DC) and radio frequency (RF) traits were found to be comparable to those of InP-based lattice-matched high-electron-mobility transistors (LM-HEMTs). However, the Pulsed I–V measurement results confirmed the presence of the fast transient charging effect, leading to a more substantial degradation in drain current observed in MHEMT. In addition, through the low-frequency noise characteristics, it was confirmed that the dominant trapping location was located in the bulk site. The slope of the 1/f noise measurement indicated that the primary trapping site was in proximity to the bulk traps. The carrier-number-fluctuation (CNF) model was employed to extract the bulk trap density (N_t). For the LM-HEMTs, the value was at 3.27 × 10¹⁶ eV⁻¹·cm⁻³, while for the MHEMT, it was 3.56 × 10¹⁷ eV⁻¹·cm⁻³. Full article

In this article, the particle irradiation effect of a lightly doped Gaussian source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET) is discussed. In the irradiation phenomenon, heavy ion produces a series of electron-hole pairs along the incident track, and then the generated transient current can overturn the logical state of the device when the number of electron-hole pairs is large enough. In the single-particle effect of DMG-GDS-HJLTFET, the carried energy is usually represented by linear energy transfer value (LET). In simulation, the effects of incident ion energy, incident angle, incident completion time, incident position and drain bias voltage on the single-particle effect of DMG-GDS-HJLTFET are investigated. On this basis, we optimize the auxiliary gate dielectric, tunneling gate length for reliability. Simulation results show HfO₂ with a large dielectric constant should be selected as the auxiliary gate dielectric in the anti-irradiation design. Larger tunneling gate leads to larger peak transient drain current and smaller tunneling gate means larger pulse width; from the point of anti-irradiation, the tunneling gate length should be selected at about 10 nm. Full article

In this study, we present a detailed analysis of trapping characteristics at the Al_xGa_1−xN/GaN interface of Al_xGa_1−xN/GaN high-electron-mobility transistors (HEMTs) with reliability assessments, demonstrating how the composition of the Al in the Al_xGa_1−xN barrier impacts the performance of the device. Reliability instability assessment in two different Al_xGa_1−xN/GaN HEMTs [x = 0.25, 0.45] using a single-pulse I_D–V_D characterization technique revealed higher drain-current degradation (∆I_D) with pulse time for Al_0.45Ga_0.55N/GaN devices which correlates to the fast-transient charge-trapping in the defect sites near the interface of Al_xGa_1−xN/GaN. Constant voltage stress (CVS) measurement was used to analyze the charge-trapping phenomena of the channel carriers for long-term reliability testing. Al_0.45Ga_0.55N/GaN devices exhibited higher-threshold voltage shifting (∆V_T) caused by stress electric fields, verifying the interfacial deterioration phenomenon. Defect sites near the interface of the AlGaN barrier responded to the stress electric fields and captured channel electrons—resulting in these charging effects that could be partially reversed using recovery voltages. The quantitative extraction of volume trap density (N_t) using 1/f low-frequency noise characterizations unveiled a 40% reduced N_t for the Al_0.25Ga_0.75N/GaN device, further verifying the higher trapping phenomena in the Al_0.45Ga_0.55N barrier caused by the rougher Al_0.45Ga_0.55N/GaN interface. Full article

Extracting relevant data from real-world experiments is often challenging with intrinsic materials and device property dispersion, such as in organic electronics. However, multivariate data analysis can often be a mean to circumvent this and to extract more information when larger datasets are used with learning algorithms instead of physical models. Here, we report on identifying relevant information descriptors for organic electrochemical transistors (OECTs) to classify aqueous electrolytes by ionic composition. Applying periodical gate pulses at different voltage magnitudes, we extracted a reduced number of nonredundant descriptors from the rich drain-current dynamics, which provide enough information to cluster electrochemical data by principal component analysis between Ca²⁺-, K⁺-, and Na⁺-rich electrolytes. With six current values obtained at the appropriate time domain of the device charge/discharge transient, one can identify the cationic identity of a locally probed transient current with only a single micrometric device. Applied to OECT-based neural sensors, this analysis demonstrates the capability for a single nonselective device to retrieve the rich ionic identity of neural activity at the scale of each neuron individually when learning algorithms are applied to the device physics. Full article

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB^®/Simulink^® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented. Full article

Single-event effects (SEE) are an important index of radiation resistance for fully depleted silicon on insulator (FDSOI) devices. The research into traditional FDSOI devices is based on simulation software, which is time consuming, requires a large amount of calculation, and has complex operations. In this paper, a prediction method for the SEE of FDSOI devices based on deep learning is proposed. The characterization parameters of SEE can be obtained quickly and accurately by inputting different particle incident conditions. The goodness of fit of the network curve for predicting drain transient current pulses can reach 0.996, and the accuracy of predicting the peak value of drain transient current and total collected charge can reach 94.00% and 96.95%, respectively. Compared with TCAD Sentaurus software, the simulation speed is increased by 5.10 × 10² and 1.38 × 10³ times, respectively. This method can significantly reduce the computational cost, improve the simulation speed, and provide a new feasible method for the study of the single-event effect in FDSOI devices. Full article

Thanks to high-current densities and cutoff frequencies, short-channel length AlGaN/GaN HEMTs are a promising technology solution for implementing RF power amplifiers in 5G front-end modules. These devices, however, might suffer from current collapse due to trapping effects, leading to compressed output power. Here, we investigate the trap dynamic response in 0.15 μm GaN HEMTs by means of pulsed I-V characterization and drain current transients (DCTs). Pulsed I-V curves reveal an almost absent gate-lag but significant current collapse when pulsing both gate and drain voltages. The thermally activated Arrhenius process (with E_A ≈ 0.55 eV) observed during DCT measurements after a short trap-filling pulse (i.e., 1 μs) indicates that current collapse is induced by deep trap states associated with iron (Fe) doping present in the buffer. Interestingly, analogous DCT characterization carried out after a long trap-filling pulse (i.e., 100 s) revealed yet another process with time constants of about 1–2 s and which was approximately independent of temperature. We reproduced the experimentally observed results with two-dimensional device simulations by modeling the T-independent process as the charging of the interface between the passivation and the AlGaN barrier following electron injection from the gate. Full article

In this paper, we compare and discuss the main techniques for the analysis of the dynamic performance of GaN-based transistors. The pulsed current-voltage characterization provides information on the effect of different trapping voltages on various bias points of the device under test, leading to the detection of all the possible effects, as well as to the choice of the optimal filling and measure bias conditions in other techniques. The drain current transients use one of the identified bias configurations to extract information on the deep level signature responsible for the performance variation and, thus, they can pinpoint the corresponding physical crystal lattice configuration, providing useful information to the growers on how the issue can be solved. Finally, given the complex interplay between the filling and emission time constants, the gate frequency sweeps can be used to obtain the real performance in the target operating condition. Full article

This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 $\mathsf{\mu }$ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation. Full article