Search Results (29)

This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a voltage buffer in cascading configurations. A thorough non-ideal analysis, accounting for parasitic impedances and the non-ideal gains of the active module, shows negligible effects on the filter performance. Furthermore, a sensitivity analysis with respect to both active and passive components further validates the robustness of the design. The proposed all-pass filter is validated by Cadence PSPICE simulations, utilizing 0.18 µm TSMC CMOS process parameter and ±0.9 V power supply, including Monte Carlo analysis and temperature variations. Additionally, experimental validation is carried out using commercially available IC AD844, showing great consistency between theoretical and experimental results. Resistor-less realization of the proposed filter provides tunability feature. A quadrature sinusoidal oscillator is presented to validate the proposed structure. The introduced circuit provides a simple and effective solution for low-power and compact analog signal processing applications. Full article

This paper presents the design and implementation of a 6-bit high-precision active vector-sum phase shifter (PS) operating in the E-band, fabricated using a 40 nm CMOS process. To generate high-quality in-phase and quadrature (I/Q) signals, a folded transformer-based quadrature generator circuit (QGC) employing inductive compensation is developed. Additionally, the series peaking enhancement technique is applied to improve overall gain and effectively extend the bandwidth. Measurement results demonstrate that the phase shifter achieves a 3 dB bandwidth from 72.3 GHz to 82.3 GHz. Within this range, the measured RMS phase error is merely 1.78–2.55 degrees without calibration, and the RMS gain error is 0.6–0.75 dB. The core area of the proposed phase shifter is 940 μm × 280 μm, and it consumes 57.2 mW of power with a 1.1 V supply. Full article

This study introduces an electronically tunable resistorless mixed-mode universal filter and dual-mode quadrature oscillator configuration utilizing merely two voltage differencing gain amplifiers and two grounded capacitors. The suggested filter can perform all generic biquadratic filter functions in all four modes: voltage mode, trans-admittance mode, current mode, and trans-impedance mode, while utilizing the same design. The pole frequency and the quality factor can be tuned electronically and orthogonally by means of the transconductances of the voltage differencing gain amplifier. The dual-mode quadrature oscillator featuring both voltage and current outputs can also be obtained from the proposed filter core. It additionally provides separate electronic control of the oscillation condition and frequency. Several PSPICE simulations with the TSMC 0.18 μm CMOS model confirm the feasibility of the proposed configurations. Both proposed circuits were experimentally evaluated using commercially available integrated circuit LM13600s. Both simulation and experimental results have validated the performance of the design. Full article

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm², with a core area of 0.165 mm², and consumes 19.5 mW of power from a 2.5 V supply. Full article

Phase shifters are essential components of phased array systems, which are crucial to radar and wireless communication systems. New-generation telecommunication and radar systems often require strict phase shifter performance metrics, such as phase resolution and bandwidth, to perform fine beam scanning, which helps increase pointing accuracy. Meanwhile, practical vector modulator phase shifters, which employ quadrature signal operation, typically have digital control below 7 bits. In this regard, a vector modulator phase shifter based on non-quadrature signal operation and covering the lower S-band and upper C-band is proposed and implemented in this work. The proof-of-concept printed circuit board (PCB) prototype exhibits more than 360° continuous phase shift with more than 50% fractional bandwidth. In addition, it achieves a median gain of 0.8 dB and a size of 0.9 ${{\lambda }_g}^2$ with the inclusion of an output gain-block amplifier. The relatively wider bandwidth, smaller size, and fine resolution of the proposed phase shifter approach make it a potential candidate for new-generation ultrawideband communication and radar systems. Full article

The multifunctionality feature of graphene field-effect transistors (GFETs) is exploited here to design circuit building blocks of high-data-rate modulators by using a physics-based compact model. Educated device performance projections are obtained with the experimentally calibrated model and used to choose an appropriate improved feasible GFET for these applications. Phase-shift and frequency-shift keying (PSK and FSK) modulation schemes are obtained with $0.6$ $\mathrm{G}$$\mathrm{Hz}$ GFET-based multifunctional circuits used alternatively in different operation modes: inverting and in-phase amplification and frequency multiplication. An adequate baseband signal applied to the transistors’ input also serves to enhance the device and circuit performance reproducibility since the impact of traps is diminished. Quadrature PSK is also achieved by combining two GFET-based multifunctional circuits. This device circuit co-design proposal intends to boost the heterogeneous implementation of graphene devices with incumbent technologies into a single chip: the baseband pulses can be generated with CMOS technology as a front end of line and the multifunctional GFET-based circuits as a back end of line. Full article

Developing a miniatured laser vibrometer becomes important for many engineering areas, such as experimental and operational modal analyses, model validation, and structural health monitoring. Due to its compact size and light weight, a miniatured laser vibrometer can be attached to various mobilized platforms, such as an unmanned aerial vehicle and a robotic arm whose payloads can usually not be large, to achieve a flexible vibration measurement capability. However, integrating optics into a miniaturized laser vibrometer presents several challenges. These include signal interference from ghost reflectance signals generated by the sub-components of integrated photonics, polarization effects caused by waveguide structures, wavelength drifting due to the semiconductor laser, and the poorer noise characteristics of an integrated laser chip compared to a non-integrated circuit. This work proposes a novel chip-based high-precision laser vibrometer by incorporating two or more sets of quadrature demodulation networks into its design. An additional set of quadrature demodulation networks with a distinct reference arm delay line length can be used to conduct real-time compensation to mitigate linear interference caused by temperature and environmental variations. A series of vibration measurements with frequencies ranging from 0.1 Hz to 1 MHz were conducted using the proposed laser vibrometer to show its repeatability and accuracy in vibration and ultrasonic vibration measurements, and its robustness to test surface conditions. The proposed laser vibrometer has the advantage of directly measuring the displacement response of a vibrating structure rather than integrating its velocity response to yield the measured displacement with a conventional laser Doppler vibrometer. Full article

The armature reaction of the hybrid excitation starter generator (HESG) under load conditions will affect the distribution of the main magnetic field and the output performance. However, using the conventional field-circuit combination method to study the armature reaction has the problem of low accuracy and inaccurate influencing factors. Therefore, this paper proposed a graphical method to analyze the armature reaction and a new type of HESG with a combined-pole permanent magnet (PM) rotor and claw-pole electromagnetic rotor. The analytical formula of the voltage regulation rate under the armature reaction was derived using the graphical method. The main influencing parameters of the armature reaction magnetic field (ARMF) were analyzed, and the overall output performance was analyzed using finite element software. On this basis, comparison analyses before and after optimization and the prototype test were carried out. The results show that the direct-axis armature reaction reactance, quadrature-axis armature reaction reactance, and voltage regulation rate of the optimized HESG were significantly reduced, the output voltage range of the whole machine was wide, and the voltage regulation performance was good. Full article

This paper proposes a novel orthogonal frequency division multiplexing (OFDM) optical access scheme based on bit reconstruction. In this method, correlation is introduced into the data information of optical line terminals (OLT) through the logical coding circuits and partition mapping. Even after passing through the optical fibre channel, the strong correlation after bit reconstruction can still be used in the optical network unit (ONU) for reliable decoding. In the simulation experiments, a 60 Gbit/s bit reconstruction 64 quadrature amplitude modulation (QAM) OFDM signal was successfully transmitted over a 10/20 km single-mode fibre (SMF). The simulation results show that the proposed scheme can effectively achieve reliable transmission with gains of about 1.3 dB and 0.51 dB at a 20% soft decision-forward error correction (SD-FEC) threshold, respectively. The proposed scheme is a promising candidate for a next-generation passive optical network (NGPON) solution. Full article

This paper proposes a low-noise interface application-specific integrated circuit (ASIC) for a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) which operates in force-to-rebalance (FTR) mode. The ASIC employs an analog closed-loop control scheme which incorporates a self-excited drive loop, a rate loop and a quadrature loop. A ΣΔ modulator and a digital filter are also contained in the design to digitize the analog output besides the control loops. The clocks for the modulator and digital circuits are both generated by the self-clocking circuit, which avoids the requirement of additional quartz crystal. A system-level noise model is established to determine the contribution of each noise source in order to reduce the noise at the output. A noise optimization solution suitable for chip integration is proposed based on system-level analysis, which can effectively avoid the effects of the 1/f noise of the PI amplifier and the white noise of the feedback element. A performance of 0.0075°/√h angle random walk (ARW) and 0.038°/h bias instability (BI) is achieved using the proposed noise optimization method. The ASIC is fabricated in a 0.35 μm process with a die area of 4.4 mm × 4.5 mm and power consumption of 50 mW. Full article

Powerline interference (PLI) is a major disturbing factor in ground-free biopotential acquisition systems. PLI produces both common-mode and differential input voltages. The first is suppressed by a high common-mode rejection ratio of bioamplifiers. However, the differential PLI component evoked by the imbalance of electrode impedances is amplified together with the diagnostic differential biosignal. Therefore, PLI filtering is always demanded and commonly managed by analog or digital band-rejection filters. In electrocardiography (ECG), PLI filters are not ideal, inducing QRS and ST distortions as a transient reaction to steep slopes, or PLI remains when its amplitude varies and PLI frequency deviates from the notch. This study aims to minimize the filter errors in wide deviation ranges of PLI amplitudes and frequencies, introducing a novel biopotential readout circuit with a software PLI demodulator–remodulator concept for synchronous processing of both differential-mode and common-mode signals. A closed-loop digital synchronous filtering (SF) algorithm is designed to subtract a PLI estimation from the differential-mode input in real time. The PLI estimation branch connected to the SF output includes four stages: (i) prefilter and QRS limiter; (ii) quadrature demodulator of the output PLI using a common-mode driven reference; (iii) two servo loops for low-pass filtering and the integration of in-phase and quadrature errors; (iv) quadrature remodulator for synthesis of the estimated PLI using the common-mode signal as a carrier frequency. A simulation study of artificially generated PLI sinusoids with frequency deviations (48–52 Hz, slew rate 0.01–0.1 Hz/s) and amplitude deviations (root mean square (r.m.s.) 50–1000 μV, slew rate 10–200 μV/s) is conducted for the optimization of SF servo loop settings with artificial signals from the CTS-ECG calibration database (10 s, 1 lead) as well as for the SF algorithm test with 40 low-noise recordings from the Physionet PTB Diagnostic ECG database (10 s, 12 leads) and CTS-ECG analytical database (10 s, 8 leads). The statistical study for the PLI frequencies (48–52 Hz, slew rate ≤ 0.1 Hz/s) and amplitudes (≤1000 μV r.m.s., slew rate ≤ 40 μV/s) show that maximal SF errors do not exceed 15 μV for any record and any lead, which satisfies the standard requirements for a peak ringing noise of < 25 μV. The signal-to-noise ratio improvement reaches 57–60 dB. SF is shown to be robust against phase shifts between differential- and common-mode PLI. Although validated for ECG signals, the presented SF algorithm is generalizable to different biopotential acquisition settings via surface electrodes (electroencephalogram, electromyogram, electrooculogram, etc.) and can benefit many diagnostic and therapeutic medical devices. Full article

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer’s LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, −35.2 dBm input-referred 1 dB compression power, and 4.8–7.1 dB noise figure across 22.5–26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0–1.5 dB to 0.02–0.19 dB, and from 10.8–23.8 to 1.1–3.2 degrees, respectively. Full article

We propose and demonstrate a new analog–digital combined high-secure optical communication system based on chaotic circuit driving, which achieves encryption in the analog and digital domains. A 3D chaotic system is used for analog domain phase encryption (ADPE) and digital domain time–frequency encryption (DDTFE) simultaneously. The ADPE is carried out by the privately chaotic signal driving the phase modulator (PM), which realizes chaotic phase encryption. The chaotic circuit comprehends highly complex nonlinear dynamics. Its size is 10 cm × 5 cm, which has the characteristics of small size and low cost. The DDTFE is performed by the frequency–time encryption of signals in the digital domain. The experimental results show that the optical physical layer encryption scheme based on analog and digital combination can successfully mask the original data. The driving signal of PM is that generated by the chaotic circuit and needs to be privately synchronized, so that the legal receiver may accurately decrypt the encrypted data and the eavesdropper is unable to intercept a valuable message. If the chaotic driving circuit produces a delay of 3 s, the bit error rate (BER) reaches more than 0.3 at the receiver. The results of experiment verify that the scheme can transmit 13.3 Gb/s 16 quadrature amplitude modulation orthogonal frequency division multiplexing (16QAM-OFDM) signal over 25 km standard single mode fiber (SSMF). This scheme achieves low-cost, high-security communication, making it a suitable foundation for high-speed, secure optical communication at the physical layer. Full article

The authors review the techniques applied to diagnose oil aging. Further, the authors put forward a new diagnostic method. It stipulates for an additional high-frequency measuring loop formed in an operating transformer. This dielcometric measuring capacitor cell includes a stray capacitance generated by the transformer winding and core. The monitoring of the dependence between the physico–technological oil parameters and the measuring cell capacity is fundamental for the procedures for determining the composition and properties of the transformer oil filling this cell. High-frequency low-voltage is the output signal. To prevent the cross-impact of low-frequency high-voltage and high-frequency low-voltage circuits, the pilot high-frequency low-voltage is excited by a special coupling capacitor; the output to the power feeder is conducted through an appropriate low-frequency choke, where the measuring capacitor cell does not disturb the normal transformer operation. The key physical processes used for the monitoring are analyzed and described in detail. The authors develop an algorithm to compute the current resistances of both the transformer oil and its impurities. The transformer state is estimated by comparing the parameters specified with preset permissible limits. A structure flowchart based on two synchronous quadrature detectors is proposed for a high-frequency measuring loop. The monitoring system considered allows for determining the following insulating oil properties by using the algorithm for processing the recorded data: moisture content; dielectric losses due to the accumulation of aging products in the oil and its pollution; and the content of dissolved gases in the oil. The monitoring system operability and efficiency are confirmed by appropriate experimental studies. The experiments are conducted using a TM-25-6/0.4 oil-filled transformer with a capacity of 25 kVA in a steady-state operating mode at a load current of 25 A. It is found that the proposed control system allows for identifying a critical defect of increased moisture content in the oil with no more than 10% error, and a sensitivity threshold in the order of tenths of ppm. Full article

In recent years, electric vehicles have developed rapidly. However, many electric cars are equipped with permanent magnet synchronous motors. Permanent magnet synchronous motors have several disadvantages: For example, permanent magnets tend to demagnetize at high temperatures. Electrically excited synchronous motors have several excellent properties. First, they are cheaper because the stator and rotor of the motor only need to be wound, which is more affordable than permanent magnets for speed regulation. When the armature current reaches the maximum value, the excitation current can also be adjusted for speed regulation, which makes the speed regulation more flexible. In the case of a short circuit, the corresponding direct-axis current is smaller than the quadrature-axis current, so the fault tolerance is better. Since the traditional electric excitation motor has brushes and slips rings, sparks will be generated during commutation. Therefore, a new excitation method is adopted to make non-contact motor excitation, and the motor operation is safer and more environmentally friendly. At the same time, to ensure that the output power of the non-contact electric excitation motor remains stable, a step-down circuit and power-type fast discrete terminal sliding mode control are added after the full-bridge rectifier circuit to make the excitation current and voltage output of the motor more stable. That is, the output power reaches a steady production. In this paper, an improved sliding mode control algorithm is used to stabilize the output voltage of the non-contact excitation motor, which can still ensure the stable output of the voltage when the equivalent load changes. It is confirmed that the non-contact excitation motor can be applied to various complex situations, and the proposed algorithm is simulated and experimentally verified to verify the accuracy of the proposed algorithm. Full article