Search Results (17)

This article introduces an innovative, fully integrated low-dropout (LDO) specifically designed for low-power applications, capable of handling a wide range of load currents. By employing dynamic biasing to enhance noise performance, the LDO shows a noise equal to 14 $\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{Hz}}$ at f < 1 kHz. The LDO demonstrates remarkable efficiency with a load regulation (LDR) of 3.8 mV/A and a line regulation (LNR) of 0.71 mV/V. It boasts a rapid settling time of 1 $\mathsf{\mu }$s during load transitions up to 100 mA and a minimal quiescent current of 5 $\mathsf{\mu }$A. The regulator consistently provides a 2.6 V output for input voltages between 2.8 V and 4.8 V, with a dropout voltage of 67 mV, supporting load currents from 0 mA to 100 mA over a temperature range of −25 °C to +125 °C. The design is based on a 150 nm CMOS process to ensure high sensitivity and high performance, making it an ideal choice for battery-operated systems. Full article

A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog front-end amplifier in the 20-bit sigma-delta ADC. The PGA is a two-stage amplifier with hybrid compensation. The first stage is the recycling folded cascode amplifier with the gain-boost technique, while the second stage is the class-AB output stage. The PGA was implemented in the 0.18 μm CMOS technology and achieved a 9.44 MHz unity-gain bandwidth (UGBW) and a 57.8° phase margin when driving the capacitor of 5.9 pF. An optimum figure-of-merit (FoM) value of 905.67 has been achieved with the proposed PGA. As the front-end amplifier of a high-precision ADC, it delivers a DC gain of 162.1 dB, the equivalent input noise voltage of 301.6 nV and an offset voltage of 1.61 μV. Within the frequency range below 60 MHz, the measured PSRR of ADC is below −70 dB with an effective number of bits (ENOB), namely 20 bits. Full article

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm²), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs. Full article

This paper presents a modified current-mode vertical-cavity surface-emitting laser (VCSEL) driver as a transmitter for short-range light detection and ranging (LiDAR) sensors, where a stable bias generator is suggested with a regulated cascode current mirror circuit to provide the bias current of 1 mA with a trivial deviation of 5.4%, even at the worst-case process–voltage–temperature (PVT) variations. Also, a modified current-steering logic circuit is exploited with N-type MOSFET (NMOS) switches to deliver the modulation currents of 0.1~10 mA_pp to the VCSEL diode simultaneously, with no overshoot distortions. Post-layout simulations of the modified current-mode VCSEL driver (m-CMVD), using 180 nm CMOS technology, demonstrate very large and clean output pulses with significantly reduced signal distortions. Hereby, the VCSEL diode is transformed into an equivalent circuit with a 1.6 V DC voltage and a 50 Ω resistor for circuit simulations. The proposed m-CMVD consumes a maximum of 11 mW from a 3.3 V supply voltage and the chip core occupies an area of 0.196 mm². Full article

This brief presents a continuously regulated current mirror topology capable of providing a wide range of currents with high-precision and speed control features. The circuit combines a non-linear current-mode feedback solution for fast and energy-efficient operation with an input-referred regulated-cascode configuration for precise current mirroring. The proposed implementation has an output current ranging from 100 $\mathsf{\mu }$A to 2 $\mathrm{mA}$, exhibits a fast response time of ≈100 $\mathrm{ns}$ for the full range steps, while ensuring a high power efficiency (>90%) and low current copy errors (<0.5%). Full article

This paper proposes a novel, degradation-sensitive, adaptive SST controller for cascode GaN-FETs. Unlike in traditional transformers, a semiconductor switch’s degradation and failure can compromise its robustness and integrity. It is vital to continuously monitor a switch’s health condition to adapt it to mission-critical applications. The current state-of-the-art degradation monitoring methods for power electronics systems are computationally intensive, have limited capacity to accurately identify the severity of degradation, and can be challenging to implement in real time. These methods primarily focus on conducting accelerated life testing (ALT) of individual switches and are not typically implemented for online monitoring. The proposed controller uses accelerated life testing (ALT)-based switch degradation mapping for degradation severity assessment. This controller intelligently derates the SST to (1) ensure robust operation over the SST’s lifetime and (2) achieve the optimal degradation-sensitive function. Additionally, a fast behavioral switch loss model for cascode GaN-FETs is used. This proposed fast model estimates the loss accurately without proprietary switch parasitic information. Finally, the proposed method is experimentally validated using a 5 kW cascode GaN-FET-based SST platform. Full article

In this work, a Physically Unclonable Function (PUF) based on an improved regulated cascode current mirror (IRCCM) is presented. The proposed IRCCM improves the loop-gain of the gain-boosting branch over the conventional RCCM PUF, thereby increasing the output resistance and amplifying the mismatches due to random variations. The introduction of an explicit reference current in the biasing branch of the IRCCM results in lower native unstable bits, good robustness against environmental variations and very stable power consumption. The proposed PUF has been validated through measurement results on a test-chip implemented in a 130 nm CMOS process. The PUF performance was measured for supply voltages between 0.6 and 1.2V, and temperatures ranging from 0 °C to 75 °C. A comparison against similar designs from the literature has shown that the proposed PUF exhibits state of the art performance with improved reliability under supply voltage variations. Full article

A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier and a down converter buffer, respectively. The proposed voltage buffer is designed for low distortion and low power consumption, whereas the regulated cascode is designed for low noise and high gain. The resulting TIA was fabricated in 65 nm CMOS technology for logic and mixed-mode designs, using low-threshold voltage transistors and a supply voltage of ±1.2 V. It exhibited a 52 dBΩ transimpedance gain and a 1.1 GHz bandwidth, consuming 55.3 mW using a ±1.2 V supply. Our preamplifier stage, based on a regulated cascode, was designed considering detector capacitance, bonding wire, and packaging capacitance. The voltage buffer was designed for low-power consumption and low distortion. The measured input-referred noise of the TIA was 22 pA/√Hz. The obtained total harmonic distortion of the TIA was close to 5%. In addition, the group delay is constant for the considered bandwidth. Comparisons against published results in terms of area (A), power consumption (P), bandwidth (BW), transimpedance gain (G), and noise (N) are were performed. Both figures of merit FoMs—the ratio √ (G × BW) and P × A—and FoM/N values demostrated the advantages of the proposed approach. Full article

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dB$\mathsf{\Omega }$ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 $\mathsf{\mu }$m × 225 $\mathsf{\mu }$m. Full article

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S₁₁ parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10${}^{\circ }$, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively. Full article

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified $f_T$-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/$\sqrt{Hz}$, core DC power consumption is 7.84 mW from a $V_{DDTIA}$ of 1.6 V and core area is 39 µm × 26 µm. Full article

Negative differential resistance (NDR) is inherent in many electronic devices, in which, over a specific voltage range, the current decreases with increasing voltage. Semiconductor structures with NDR have several unique properties that stimulate the search for technological and circuitry solutions in developing new semiconductor devices and circuits experiencing NDR features. This study considers two-terminal NDR electronic circuits based on multiple-output current mirrors, such as cascode, Wilson, and improved Wilson, combined with a field-effect transistor. The undoubted advantages of the proposed electronic circuits are the linearity of the current-voltage characteristics in the NDR region and the ability to regulate the value of negative resistance by changing the number of mirrored current sources. We derive equations for each proposed circuit to calculate the NDR region’s total current and differential resistance. We consider applications of NDR circuits for designing microwave single frequency oscillators and voltage-controlled oscillators. The problem of choosing the optimal oscillator topology is examined. We show that the designed oscillators based on NDR circuits with Wilson and improved Wilson multiple-output current mirrors have high efficiency and extremely low phase noise. For a single frequency oscillator consuming 33.9 mW, the phase noise is −154.6 dBc/Hz at a 100 kHz offset from a 1.310 GHz carrier. The resulting figure of merit is −221.6 dBc/Hz. The implemented oscillator prototype confirms the theoretical achievements. Full article

This paper attempts to disclose a new GaN-based device, called the P-Cascode GaN HEMT, which uses only a single gate driver to control both the D-mode GaN and PMOS transistors. The merit of this synchronous buck converter is that it can reduce the circuit complexity of the synchronous buck converter, which is widely used to provide non-isolated power for low-voltage and high-current supply to system chips; therefore, the power conversion efficiency of the converter can be improved. In addition, the high side switch using a single D-mode GaN HEMT, which has no body diode, can prevent the bi-directional flow and thus reduce the power loss and cost compared to a design based on a series of two opposite MOSFETs. The experiment shows that the proposed P-Cascode GaN HEMT efficiency is above 98% when it operates at 500 kHz with 6 W output. With the input voltage at 12 V, the synchronous buck converter provides an adjustable regulated output voltage from 1.2 V to 10 V while delivering a maximum output current of 2 A. Full article

This paper proposes a system in package (SiP) for ultrasonic ranging composed of a 4 × 8 matrix of piezoelectric micromachined ultrasonic transducers (PMUT) and an interface integrated circuit (IC). The PMUT matrix is fabricated using the PiezoMUMPS process and the IC is implemented in the AMS 0.35 µm technology. Simulation results for the PMUT are compared to the measurement results, and an equivalent circuit has been derived to allow a better approximation of the load of the PMUT on the IC. The control circuit is composed of a high-voltage pulser to drive the PMUT for transmission and of a transimpedance amplifier to amplify the received echo. The working frequency of the system is 1.5 MHz. Full article

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm. Full article