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14 pages, 14758 KB

Open AccessArticle

A 12-Bit, 10 MS/s Two-Step Sub-Ranging SAR ADC with Top-Plate Dividing

by Jaegeun Song and Chaegang Lim

Electronics 2026, 15(5), 1050; https://doi.org/10.3390/electronics15051050 - 3 Mar 2026

Viewed by 537

In this paper, a 12-bit, 10 MS/s two-step sub-ranging successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The proposed architecture enables residue amplification within a single-stage SAR ADC by dividing the top-plate sampling node, thereby avoiding the requirement for a multi-stage design. [...] Read more.

In this paper, a 12-bit, 10 MS/s two-step sub-ranging successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The proposed architecture enables residue amplification within a single-stage SAR ADC by dividing the top-plate sampling node, thereby avoiding the requirement for a multi-stage design. This structure also eliminates gain and offset mismatches between the coarse and fine conversions, enhancing robustness and linearity. Owing to the two-step operation, the total capacitance of the capacitive digital-to-analog converter (CDAC) is reduced by 86% compared to that of a conventional SAR ADC with the same unit-capacitor size. In addition, the residue amplifier drives only one-fourth of the total CDAC capacitance, significantly relaxing its power consumption. A prototype fabricated in a 65 nm CMOS process occupies an area of 252

μ

m × 227

μ

m and demonstrates a signal-to-noise and distortion ratio (SNDR) of 65.7 dB at Nyquist-rate input. The total power consumption is 227.7

μ

W under a 1.2 V supply, resulting in a Walden figure of merit (FoM) of 14.5 fJ/conversion step. These results confirm competitive performance and energy efficiency, even with the use of an analog residue amplifier. Full article

(This article belongs to the Section Circuit and Signal Processing)

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16 pages, 3151 KB

Open AccessArticle

Triple-Sampling kT/C Noise Cancellation for SAR ADCs

by Yeong Hui Kim and Jae Hoon Shim

Electronics 2026, 15(4), 805; https://doi.org/10.3390/electronics15040805 - 13 Feb 2026

Viewed by 594

Abstract

In high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs), sampling thermal (kT/C) noise represents a fundamental performance bottleneck as it remains unaffected by quantization noise shaping. While kT/C cancellation techniques exist, their efficacy is often constrained by incomplete preamplifier settling, which imposes a [...] Read more.

In high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs), sampling thermal (kT/C) noise represents a fundamental performance bottleneck as it remains unaffected by quantization noise shaping. While kT/C cancellation techniques exist, their efficacy is often constrained by incomplete preamplifier settling, which imposes a design trade-off: achieving low residual noise requires either high power consumption to increase bandwidth or an extended noise-extraction window that degrades linearity due to input signal excursions. This paper proposes a triple-sampling kT/C cancellation technique that overcomes these limitations by introducing an additional sampling phase, splitting the noise-extraction window into smaller intervals. Circuit-level periodic steady-state (PSS) and periodic noise (Pnoise) simulations demonstrate that the proposed method reduces overall input-referred noise by approximately 23% compared to a conventional cancellation scheme. Furthermore, transient noise simulations and FFT-based spectral analysis of a noise-shaping SAR ADC confirm that the proposed scheme achieves a 2.4-dB improvement in the spurious-free dynamic range (SFDR) while maintaining a comparable signal-to-noise and distortion ratio (SNDR). These enhancements are achieved with a minimal power overhead of only 1.6%. The triple-sampling approach offers a power-efficient and linear solution for high-resolution SAR ADCs. Full article

(This article belongs to the Section Circuit and Signal Processing)

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17 pages, 6734 KB

Open AccessArticle

A Fully Integrated Monolithic Monitor for Aging-Induced Leakage Current Characterization

by Emmanuel Nti Darko, Saeid Karimpour, Daniel Adjei, Kelvin Tamakloe and Degang Chen

Sensors 2026, 26(1), 64; https://doi.org/10.3390/s26010064 - 22 Dec 2025

Viewed by 635

Abstract

This paper presents a precision, wide-dynamic-range leakage current sensor tailored for in-situ monitoring of aging mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) in both active and passive components. The proposed architecture supports high-voltage stress and is fully monolithic, integrating a current-to-voltage front-end, tunable-gain [...] Read more.

This paper presents a precision, wide-dynamic-range leakage current sensor tailored for in-situ monitoring of aging mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) in both active and passive components. The proposed architecture supports high-voltage stress and is fully monolithic, integrating a current-to-voltage front-end, tunable-gain amplifier, and a successive approximation register (SAR) analog-to-digital converter (ADC). To validate the concept, a discrete-component prototype was implemented and evaluated across a leakage current range of 1 nA to 1

μ

A. The sensor achieves 12-bit resolution with measured integral non-linearity (INL) and differential non-linearity (DNL) within

\pm 1.5

LSB and

\pm 0.3

LSB, respectively. Compared to prior monitors, the design enables linear current digitization and supports high-voltage stress, features essential for accurate and scalable TDDB characterization. Applications include embedded reliability monitoring in power converters, analog building blocks, and large-scale aging test arrays. Full article

(This article belongs to the Section Electronic Sensors)

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18 pages, 12224 KB

Open AccessArticle

A Phase-Adjustable Noise-Shaping SAR ADC for Mitigating Parasitic Capacitance Effects from PIP Capacitors

by Xuelong Ouyang, Hua Kuang, Dalin Kong, Zhengxi Cheng and Honghui Yuan

Sensors 2025, 25(19), 6029; https://doi.org/10.3390/s25196029 - 1 Oct 2025

Viewed by 1203

Abstract

High parasitic capacitance from poly-insulator-poly capacitors in complementary metal oxide semiconductor (CMOS) processes presents a major bottleneck to achieving high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) in imaging systems. This study proposes a Phase-Adjustable SAR ADC that addresses this limitation through a [...] Read more.

High parasitic capacitance from poly-insulator-poly capacitors in complementary metal oxide semiconductor (CMOS) processes presents a major bottleneck to achieving high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) in imaging systems. This study proposes a Phase-Adjustable SAR ADC that addresses this limitation through a reconfigurable architecture. The design utilizes a phase-adjustable logic unit to switch between a conventional SAR mode for high-speed operation and a noise-shaping (NS) SAR mode for high-resolution conversion, actively suppressing in-band quantization noise. An improved SAR logic unit facilitates the insertion of an adjustable phase while concurrently achieving an 86% area reduction in the core logic block. A prototype was fabricated and measured in a 0.35-µm CMOS process. In conventional mode, the ADC achieved a 7.69-bit effective number of bits at 2 MS/s. By activating the noise-shaping circuitry, performance was significantly enhanced to an 11.06-bit resolution, corresponding to a signal-to-noise-and-distortion ratio (SNDR) of 68.3 dB, at a 125 kS/s sampling rate. The results demonstrate that the proposed architecture effectively leverages the trade-off between speed and accuracy, providing a practical method for realizing high-performance ADCs despite the inherent limitations of non-ideal passive components. Full article

(This article belongs to the Section Sensing and Imaging)

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15 pages, 2668 KB

Open AccessCommunication

Time-Interleaved SAR ADC in 22 nm Fully Depleted SOI CMOS

by Trace Langdon and Jeff Dix

Chips 2025, 4(4), 40; https://doi.org/10.3390/chips4040040 - 25 Sep 2025

Viewed by 2310

Abstract

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, [...] Read more.

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

(This article belongs to the Special Issue New Research in Microelectronics and Electronics)

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15 pages, 2527 KB

Open AccessArticle

A 54 µW, 0.03 mm² Event-Driven Charge-Sensitive DAQ Chip with Comparator-Gated Dynamic Acquisition in 65 nm CMOS

by Qinghao Liu, Zhou Shu, Arokiaswami Alphones and Yuan Gao

Electronics 2025, 14(14), 2766; https://doi.org/10.3390/electronics14142766 - 9 Jul 2025

Viewed by 1105

Abstract

This paper presents a low-power data acquisition (DAQ) chip tailored for impulsive charge sensing, featuring a comparator-gated dynamic acquisition (CG-DAQ) architecture. A dynamic comparator triggers both the gain stage and a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) through a shared timing path, [...] Read more.

This paper presents a low-power data acquisition (DAQ) chip tailored for impulsive charge sensing, featuring a comparator-gated dynamic acquisition (CG-DAQ) architecture. A dynamic comparator triggers both the gain stage and a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) through a shared timing path, enabling event-driven amplification and digitization. Programmable conversion gain ranging from 5 to 40 mV/pC is achieved by switching the sampling capacitance. Fabricated in TSMC 65 nm CMOS, the chip detects input charges from 0.01 to 36 pC, supports a signal bandwidth of 10 kHz to 100 kHz, and enables sampling rates up to 1 MS/s. It achieves an input-referred noise of 5.5 fC_rms and a peak signal-to-noise ratio (SNR) of 67 dB, all within a 54 μW power envelope and a compact 0.03 mm² core area. The proposed architecture facilitates accurate and energy-efficient charge-domain sensing for capacitive and piezoelectric sensor applications. Full article

(This article belongs to the Special Issue Emerging Techniques and Applications for Analog and Mixed-Signal Integrated Circuits)

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15 pages, 32541 KB

Open AccessArticle

A High-Speed 8-Bit Single-Channel SAR ADC with Tailored Bit Intervals and Split Capacitors

by Xinyu Li, Ruida Wang, Liulu He and Kentaro Yoshioka

Electronics 2025, 14(10), 2032; https://doi.org/10.3390/electronics14102032 - 16 May 2025

Viewed by 2864

Abstract

As wireless communication systems continue to demand higher data transmission rates, the need for analog-to-digital converters (ADCs) with a higher sampling rate becomes increasingly critical. However, traditional successive approximation register (SAR) ADCs operating at 1 bit/cycle often face speed limitations due to the [...] Read more.

As wireless communication systems continue to demand higher data transmission rates, the need for analog-to-digital converters (ADCs) with a higher sampling rate becomes increasingly critical. However, traditional successive approximation register (SAR) ADCs operating at 1 bit/cycle often face speed limitations due to the fixed bit intervals and comparator regeneration delays, which constrain their scalability in advanced technology nodes. To address these challenges, this paper presents a high-speed 8-bit single-channel SAR ADC featuring a novel delay generation circuit that enables tailored bit intervals (TBIs) to reduce conversion latency. A split capacitive digital-to-analog converter (CDAC) is employed to suppress input common-mode voltage shifts, while inverted dynamic latch pairs and early capacitor reset techniques are introduced to improve conversion speed. The proposed ADC is implemented in a 16 nm CMOS process, occupying only 0.0012 mm². Post-layout simulations across extreme process and temperature corners validate the robustness of the design. The TBI-ADC achieves an effective number of bits (ENOB) of 7.20 bits at Typical–Typical (TT) 25 °C with a power consumption of 6.94 mW. Furthermore, it reaches a sampling rate of 1.6 GS/s at Fast–Fast (FF) −40 °C, representing a 33% improvement over the fastest previously reported single-channel, 1 bit/cycle, 8-bit SAR ADC. Full article

(This article belongs to the Special Issue Advanced High-Performance Analog Integrated Circuits)

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22 pages, 38738 KB

Open AccessArticle

A 0.6 V 68.2 dB 0.42 µW SAR-ΣΔ ADC for ASIC Chip in 0.18 µm CMOS

by Xinyu Li, Kentaro Yoshioka, Zhongfeng Wang, Jun Lin and Congyi Zhu

Electronics 2025, 14(10), 2030; https://doi.org/10.3390/electronics14102030 - 16 May 2025

Viewed by 1513

Abstract

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in [...] Read more.

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process. Full article

(This article belongs to the Special Issue Analog/Mixed Signal Integrated Circuit Design)

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18 pages, 7054 KB

Open AccessArticle

A 13.44-Bit Low-Power SAR ADC for Brain–Computer Interface Applications

by Hongyuan Yang, Jiahao Cheong and Cheng Liu

Appl. Sci. 2025, 15(10), 5494; https://doi.org/10.3390/app15105494 - 14 May 2025

Cited by 1 | Viewed by 2443

Abstract

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power [...] Read more.

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power consumption at a supply voltage of 1.8 V, enabled by a piecewise monotonic switching scheme and dynamic logic architecture. The ADC supports a high input range of ±500 mV, making it suitable for neural signal acquisition. Through an optimized capacitive digital-to-analog converter (CDAC) array and a high-speed dynamic comparator, the ADC demonstrates a signal-to-noise-and-distortion ratio (SINAD) of 81.94 dB and a spurious-free dynamic range (SFDR) of 91.69 dBc at a sampling rate of 320 kS/s. Experimental results validate the design’s superior performance in terms of low-power operation, high resolution, and moderate sampling rate, positioning it as a competitive solution for high-density integration and precision neural signal processing in next-generation BCI systems. Full article

(This article belongs to the Special Issue Low-Power Integrated Circuit Design and Application)

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12 pages, 10567 KB

Open AccessArticle

A Low-Power, Auto-DC-Suppressed Photoplethysmography Readout System with Differential Current Mirrors and Wide Common-Mode Input Range Successive Approximation Register Analog-to-Digital Converter

by Chanyoung Son, Seok-Tae Koh and Hyuntak Jeon

Micromachines 2025, 16(4), 398; https://doi.org/10.3390/mi16040398 - 29 Mar 2025

Viewed by 1511

Abstract

This paper presents a low-power photoplethysmography (PPG) readout system designed for wearable health monitoring. The system employs a differential current mirror (DCM) to convert single-ended PPG currents into differential voltages, inherently suppressing DC components. A wide common-mode input range (WCMIR) SAR ADC processes [...] Read more.

This paper presents a low-power photoplethysmography (PPG) readout system designed for wearable health monitoring. The system employs a differential current mirror (DCM) to convert single-ended PPG currents into differential voltages, inherently suppressing DC components. A wide common-mode input range (WCMIR) SAR ADC processes the differential signals, ensuring accurate analog-to-digital conversion. The DCM eliminates the need for DC cancelation loops, simplifying the design and reducing power consumption. Implemented in a 0.18 µm CMOS process, the system occupies only 0.30 mm², making it suitable for multi-channel applications. The system achieves over 60 dB DC dynamic range and consumes only 9.6 µW, demonstrating its efficiency for portable devices. The simulation results validate its ability to process PPG signals across various conditions, offering a scalable solution for advanced biomedical sensing platforms. Full article

(This article belongs to the Special Issue Micro/Nano Sensors: Fabrication and Applications)

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17 pages, 2275 KB

Open AccessArticle

Enhanced Linearity in Intracranial Pressure Monitoring System Through Sample Isolation Bridge ROIC

by Shaopeng Yao, Qiang Shan, Jinjin Xiao, Zihui Wei and Shuilong Huang

Appl. Sci. 2025, 15(6), 3008; https://doi.org/10.3390/app15063008 - 11 Mar 2025

Cited by 1 | Viewed by 1407

Abstract

This study presents a sample isolation bridge readout integrated circuit (ROIC) specifically designed for intracranial pressure (ICP) monitoring systems. The ROIC consists of an instrumentation amplifier (IA) and a successive approximation register (SAR) analog-to-digital converter (ADC). Additionally, the output of the IA is [...] Read more.

This study presents a sample isolation bridge readout integrated circuit (ROIC) specifically designed for intracranial pressure (ICP) monitoring systems. The ROIC consists of an instrumentation amplifier (IA) and a successive approximation register (SAR) analog-to-digital converter (ADC). Additionally, the output of the IA is isolated to protect against output spikes that could compromise the linearity and stability of the ROIC. Both traditional and proposed ROIC circuits are fabricated using 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology. The peak signal-to-noise ratio (SNR) for the traditional ROIC is 40.9 dB, while the peak signal-to-noise and distortion ratio (SNDR) is measured at 40.1 dB. In contrast, the proposed ROIC, which incorporates the SAR ADC, achieves a peak SNR of 54.6 dB and a peak SNDR of 51.8 dB, demonstrating a significant improvement in linearity. The new ROIC consumes 39.5 µA of current from a 1.8 V power supply and occupies a chip core area of only 0.27 mm². Full article

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14 pages, 882 KB

Open AccessArticle

An 11-Bit Single-Slope/Successive Approximation Register Analog-to-Digital Converters with On-Chip Fine Step Range Calibration for CMOS Image Sensors

by Seong-Jun Byun, Jee-Taeck Seo, Tae-Hyun Kim, Jeong-Hun Lee, Young-Kyu Kim and Kwang-Hyun Baek

Electronics 2025, 14(1), 83; https://doi.org/10.3390/electronics14010083 - 27 Dec 2024

Cited by 3 | Viewed by 2178

Abstract

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely [...] Read more.

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (

{FOM}_{W}

) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications. Full article

(This article belongs to the Section Circuit and Signal Processing)

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15 pages, 2565 KB

Open AccessTutorial

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

by Zhaoyang Shen, Shiheng Yang and Jiaxin Liu

Chips 2024, 3(4), 296-310; https://doi.org/10.3390/chips3040015 - 1 Oct 2024

Viewed by 4245

Abstract

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (

Δ Σ

) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. [...] Read more.

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (

Δ Σ

) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC. Full article

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20 pages, 3808 KB

Open AccessArticle

Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application

by Muh-Tian Shiue, Yu-Fan Lo and Chih-Yao Jung

Electronics 2024, 13(17), 3549; https://doi.org/10.3390/electronics13173549 - 6 Sep 2024

Cited by 4 | Viewed by 3503

Abstract

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using [...] Read more.

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18

μ

m complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm² (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7

μ

W, with the core power consumption at 932 nW. Full article

(This article belongs to the Special Issue Analog and Mixed-Signal Circuit Designs and Their Applications)

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14 pages, 2073 KB

Open AccessArticle

Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain

by Shichao Jia, Tianchun Ye and Shimao Xiao

Electronics 2024, 13(17), 3400; https://doi.org/10.3390/electronics13173400 - 27 Aug 2024

Viewed by 2655

Abstract

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C [...] Read more.

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical analysis of the performance enhancement based on noise and other considerations is presented. Full article

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