J. Low Power Electron. Appl., Volume 11, Issue 1 (March 2021) – 13 articles

Optimizing software to become (more) energy efficient is an important concern for the software industry. Although several techniques have been proposed to measure energy consumption within software engineering, little work has specifically addressed Software Product Lines (SPLs). SPLs are a widely used software development approach, where the core concept is to study the systematic development of products that can be deployed in a variable way, e.g., to include different features for different clients. The traditional approach for measuring energy consumption in SPLs is to generate and individually measure all products, which, given their large number, is impractical. We present a technique, implemented in a tool, to statically estimate the worst-case energy consumption for SPLs. The goal is to reason about energy consumption in all products of a SPL, without having to individually analyze each product. Our technique combines static analysis and worst-case prediction with energy consumption analysis, in order to analyze products in a feature-sensitive manner: a feature that is used in several products is analyzed only once, while the energy consumption is estimated once per product. This paper describes not only our previous work on worst-case prediction, for comprehensibility, but also a significant extension of such work. This extension has been realized in two different axis: firstly, we incorporated in our methodology a simulated annealing algorithm to improve our worst-case energy consumption estimation. Secondly, we evaluated our new approach in four real-world SPLs, containing a total of 99 software products. Our new results show that our technique is able to estimate the worst-case energy consumption with a mean error percentage of 17.3% and standard deviation of 11.2%. Full article

This paper analyzes how to improve the precision of ionoacoustic proton range verification by optimizing the analog signal processing stages with particular emphasis on analog filters. The ionoacoustic technique allows one to spatially detect the proton beam penetration depth/range in a water absorber, with interesting possible applications in real-time beam monitoring during hadron therapy treatments. The state of the art uses nonoptimized detectors that have low signal quality and thus require a higher total dose, which is not compatible with clinical applications. For these reasons, a comprehensive analysis of acoustic signal bandwidth, signal-to-noise-ratio and noise power/bandwidth will be presented. The correlation between these signal-quality parameters with maximum achievable proton range measurement precision will be discussed. In particular, the use of an optimized analog filter allows one to decrease the dose required to achieve a given precision by as much as 98.4% compared to a nonoptimized filter approach. Full article

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature. Full article

This work introduces a light harvesting system with battery management. In contrast to relevant solutions that operate in limited ranges, the proposed system covers a wide operating input power range from 10 uW up to 300 mW. Specifically, experimental results highlight that, combined with a 73 × 94 mm flexible light harvester, it can harness light in a range from 50 LUX (indoor lighting) up to 120,000 LUX (outdoor lighting). The introduced system consists of a boost converter and an ultra-low power microcontroller (MCU). The MCU performs Global Maximum Power Point Tracking (GMPPT), using a resistor-free time-based input power sensing method, to calculate the input power of the converter, which does not interfere with the operation of the boost converter. The efficiency of the GMPPT system was evaluated with detailed experimentation, where we achieved 99.75% average GMPPT tracking efficiency while consuming only 73.5 uW at 4.2 V. Full article

In this paper, we extend the application of the Quasi-Static Memdiode model to the realistic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) intended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-written characters of the MNIST database, we evaluate the degradation of the inference accuracy due to the interconnection resistances for MLPs involving up to three hidden neural layers. Two approaches to reduce the impact of the line resistance are considered and implemented in our simulations, they are the inclusion of an iterative calibration algorithm and the partitioning of the synaptic layers into smaller blocks. The obtained results indicate that MLPs are more sensitive to the line resistance effect than SLPs and that partitioning is the most effective way to minimize the impact of high line resistance values. Full article

With the advancement of technology scaling, multi/many-core platforms are getting more attention in embedded systems due to the ever-increasing performance requirements and power efficiency. This feature size scaling, along with architectural innovations, has dramatically exacerbated the rate of manufacturing defects and physical fault-rates. As a result, in addition to providing high parallelism, such hardware platforms have introduced increasing unreliability into the system. Such systems need to be well designed to ensure long-term and application-specific reliability, especially in mixed-criticality systems, where incorrect execution of applications may cause catastrophic consequences. However, the optimal allocation of applications/tasks on multi/many-core platforms is an increasingly complex problem. Therefore, reliability-aware resource management is crucial while ensuring the application-specific Quality-of-Service (QoS) requirements and optimizing other system-level performance goals. This article presents a survey of recent works that focus on reliability-aware resource management in multi-/many-core systems. We first present an overview of reliability in electronic systems, associated fault models and the various system models used in related research. Then, we present recent published articles primarily focusing on aspects such as application-specific reliability optimization, mixed-criticality awareness, and hardware resource heterogeneity. To underscore the techniques’ differences, we classify them based on the design space exploration. In the end, we briefly discuss the upcoming trends and open challenges within the domain of reliability-aware resource management for future research. Full article

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions. Full article

We use commercial magnetic memory to realize morphable security primitives, a Physically Unclonable Function (PUF) and a True Random Number Generator (TRNG). The PUF realized by manipulating the write time and the TRNG is realized by tweaking the number of write pulses. Our analysis indicates that more than 75% bits in the PUF are unusable without any correction due to their inability to exhibit any randomness. We exploit temporal randomness of working columns to fix the unusable columns and write latency to fix the unusable rows during the enrollment. The intra-HD, inter-HD, energy, bandwidth and area of the proposed PUF are found to be 0, 46.25%, 0.14 pJ/bit, 0.34 Gbit/s and 0.385 μm²/bit (including peripherals) respectively. The proposed TRNG provides all possible outcomes with a standard deviation of 0.0062, correlation coefficient of 0.05 and an entropy of 0.95. The energy, bandwidth and area of the proposed TRNG is found to be 0.41 pJ/bit, 0.12 Gbit/s and 0.769 μm²/bit (including peripherals). The performance of the proposed TRNG has also been tested with NIST test suite. The proposed designs are compared with other magnetic PUFs and TRNGs from other literature. Full article

Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array. Full article

With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was V_analog (1.5 V) and V_digital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step. Full article

The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry. Full article

Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power consumption design space without affecting other specifications regarding the main OTA. This technique lends itself to be employed jointly with advanced OTA topologies in order to compose a highly energy efficient OTA/SRE system. However, insights in design choices such as power optimization are still missing for such systems. Here we discuss system level choices with the help of a simple model. Using precise electrical simulations, we demonstrate energy savings greater than 30% for different OTA/SRE systems implemented in a standard 180-nm CMOS technology. Full article