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J. Low Power Electron. Appl., Volume 3, Issue 4 (December 2013), Pages 300-384

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Research

Open AccessArticle Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology
J. Low Power Electron. Appl. 2013, 3(4), 300-336; doi:10.3390/jlpea3040300
Received: 6 August 2013 / Revised: 20 September 2013 / Accepted: 12 October 2013 / Published: 25 October 2013
Cited by 2 | PDF Full-text (648 KB) | HTML Full-text | XML Full-text
Abstract
As portable devices become more ubiquitous, data security in these devices is becoming increasingly important. Traditional circuit design techniques leave otherwise secure systems vulnerable due to the characteristics of the hardware implementation, rather than weaknesses in the security algorithms. These characteristics, called [...] Read more.
As portable devices become more ubiquitous, data security in these devices is becoming increasingly important. Traditional circuit design techniques leave otherwise secure systems vulnerable due to the characteristics of the hardware implementation, rather than weaknesses in the security algorithms. These characteristics, called side-channels, are exploitable because they can be measured and correlated with processed data, potentially giving an attacker insight into the device’s secret data. Alternative design techniques such as dual-rail asynchronous designs are capable of minimizing these potential side-channels by decoupling them from the data being processed. However, these techniques are either expensive to implement compared to standard designs or leave exploitable imbalances in the dual-rail implementation itself. Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L) offers security by balancing side-channels both in general and between the dual-rail signals themselves, as well as reduction in circuit overhead compared to previous secure design techniques. Results show that the Advanced Encryption Standard (AES) cores designed using MTD3L exhibit similar security to previous secure techniques with substantially less area and energy overhead. Full article
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Open AccessArticle Hardware Implementation of an Automatic Rendering Tone Mapping Algorithm for a Wide Dynamic Range Display
J. Low Power Electron. Appl. 2013, 3(4), 337-367; doi:10.3390/jlpea3040337
Received: 24 June 2013 / Revised: 12 August 2013 / Accepted: 9 September 2013 / Published: 29 October 2013
Cited by 2 | PDF Full-text (45726 KB) | HTML Full-text | XML Full-text
Abstract
Tone mapping algorithms are used to adapt captured wide dynamic range (WDR) scenes to the limited dynamic range of available display devices. Although there are several tone mapping algorithms available, most of them require manual tuning of their rendering parameters. In addition, [...] Read more.
Tone mapping algorithms are used to adapt captured wide dynamic range (WDR) scenes to the limited dynamic range of available display devices. Although there are several tone mapping algorithms available, most of them require manual tuning of their rendering parameters. In addition, the high complexities of some of these algorithms make it difficult to implement efficient real-time hardware systems. In this work, a real-time hardware implementation of an exponent-based tone mapping algorithm is presented. The algorithm performs a mixture of both global and local compression on colored WDR images. An automatic parameter selector has been proposed for the tone mapping algorithm in order to achieve good tone-mapped images without manual reconfiguration of the algorithm for each WDR image. Both algorithms are described in Verilog and synthesized for a field programmable gate array (FPGA). The hardware architecture employs a combination of parallelism and system pipelining, so as to achieve a high performance in power consumption, hardware resources usage and processing speed. Results show that the hardware architecture produces images of good visual quality that can be compared to software-based tone mapping algorithms. High peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) scores were obtained when the results were compared with output images obtained from software simulations using MATLAB. Full article
Open AccessArticle Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits
J. Low Power Electron. Appl. 2013, 3(4), 368-384; doi:10.3390/jlpea3040368
Received: 30 September 2013 / Revised: 29 November 2013 / Accepted: 6 December 2013 / Published: 16 December 2013
Cited by 3 | PDF Full-text (412 KB) | HTML Full-text | XML Full-text
Abstract
This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such [...] Read more.
This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1-dimensional reduced order model (ROM) of the switch; the results given by this simplified model are compared to classical CMOS-based, and sub-threshold CMOS-based adiabatic logic circuits. NEMS-based circuits and CMOS-based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency. Full article
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)

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