Next Issue
Previous Issue

Table of Contents

J. Low Power Electron. Appl., Volume 3, Issue 3 (September 2013), Pages 215-299

  • Issues are regarded as officially published after their release is announced to the table of contents alert mailing list.
  • You may sign up for e-mail alerts to receive table of contents of newly released issues.
  • PDF is the official format for papers published in both, html and pdf forms. To view the papers in pdf format, click on the "PDF Full-text" link, and use the free Adobe Readerexternal link to open them.
View options order results:
result details:
Displaying articles 1-5
Export citation of selected articles as:

Research

Jump to: Review

Open AccessArticle Sub-Threshold Standard Cell Sizing Methodology and Library Comparison
J. Low Power Electron. Appl. 2013, 3(3), 233-249; doi:10.3390/jlpea3030233
Received: 4 February 2013 / Revised: 29 May 2013 / Accepted: 25 June 2013 / Published: 15 July 2013
Cited by 2 | PDF Full-text (453 KB) | HTML Full-text | XML Full-text
Abstract
Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold [...] Read more.
Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of [1,2] on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this paper, the equivalent N and P networks are derived based on the best and worst case transition times. The slack available in the best-case timing arc is reduced by using smaller transistors on that path, while the timing of the worst-case timing arc is improved by using bigger transistors. The optimization is done such that the overall area remains constant with regard to the area before optimization. Two sizing styles are applied, one is based on both transistor width and length tuning, and the other one is based on width tuning only. Compared to super-threshold libraries, at 0.3 V, the proposed libraries achieve 49% and 89% average cell timing improvement and 55% and 31% power delay product improvement at 40 nm and 90 nm respectively. From ITC (International Test Conference 99) benchmark circuit synthesis results, at 0.3 V the proposed library achieves up to 52% timing improvement and 53% power savings in the 40 nm technology node. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessArticle A Low Power CMOS Imaging System with Smart Image Capture and Adaptive Complexity 2D-DCT Calculation
J. Low Power Electron. Appl. 2013, 3(3), 267-278; doi:10.3390/jlpea3030267
Received: 4 February 2013 / Revised: 1 June 2013 / Accepted: 29 July 2013 / Published: 8 August 2013
PDF Full-text (611 KB) | HTML Full-text | XML Full-text
Abstract
A novel low power CMOS imaging system with smart image capture and adaptive complexity 2D-Discrete Cosine Transform (DCT) is proposed. Compared with the existing imaging systems, it involves the smart image capture and image processing stages cooperating together and is very efficient. [...] Read more.
A novel low power CMOS imaging system with smart image capture and adaptive complexity 2D-Discrete Cosine Transform (DCT) is proposed. Compared with the existing imaging systems, it involves the smart image capture and image processing stages cooperating together and is very efficient. The type of each 8 × 8 block is determined during the image capture stage, and then input into the DCT block, along with the pixel values. The 2D-DCT calculation has adaptive computation complexity according to block types. Since the block type prediction has been moved to the front end, no extra time or calculation is needed during image processing or image capturing for prediction. The image sensor with block type decision circuit is implemented in TSMC 0.18 µm CMOS technology. The adaptive complexity 2D-DCT compression is implemented based on Cyclone EP1C20F400C8 device. The performance including the image quality of the reconstructed picture and the power consumption of the imaging system are compared to those of traditional CMOS imaging systems to show the benefit of the proposed low power algorithm. According to simulation, up to 46% of power consumption can be saved during 2D DCT calculation without extra loss of image quality for the reconstructed pictures compared with the conventional compression methods. Full article
(This article belongs to the Special Issue Energy Efficient Sensors and Applications)
Open AccessArticle Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System
J. Low Power Electron. Appl. 2013, 3(3), 279-299; doi:10.3390/jlpea3030279
Received: 6 March 2013 / Revised: 8 July 2013 / Accepted: 6 August 2013 / Published: 9 September 2013
Cited by 1 | PDF Full-text (1131 KB) | HTML Full-text | XML Full-text
Abstract
Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain [...] Read more.
Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-gain, low-noise integrated neuronal amplifier (NA) with the capability of recording local field potentials (LFP) and spike activity is presented. In vitro and in vivo characterizations of the tissue/electrode interface, with equivalent impedance as an electrical model for recording in the LFP band using macro-electrodes for rodents, contribute to the NA design constraints. The NA occupies 0.15 mm2 and dissipates 6.73 µW, and was fabricated using a 0.35 µm CMOS process. Test-bench validation indicates that the NA provides a mid-band gain of 20 dB and achieves a low input-referred noise of 4 µVRMS. Ability of the NA to perform spike recording in test-bench experiments is presented. Additionally, an awake and freely moving rodent setup was used to illustrate the integrated NA ability to record LFPs, paving the pathway for future implantable systems for neuromodulation. Full article

Review

Jump to: Research

Open AccessReview A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications
J. Low Power Electron. Appl. 2013, 3(3), 215-232; doi:10.3390/jlpea3030215
Received: 18 March 2013 / Revised: 1 June 2013 / Accepted: 5 June 2013 / Published: 24 June 2013
Cited by 2 | PDF Full-text (740 KB) | HTML Full-text | XML Full-text
Abstract
This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and [...] Read more.
This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
Open AccessReview Exploration of Charge Recycling DC-DC Conversion Using a Switched Capacitor Regulator
J. Low Power Electron. Appl. 2013, 3(3), 250-266; doi:10.3390/jlpea3030250
Received: 6 January 2013 / Revised: 5 July 2013 / Accepted: 9 July 2013 / Published: 29 July 2013
PDF Full-text (492 KB) | HTML Full-text | XML Full-text
Abstract
The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. [...] Read more.
The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. The idea is to supply nominal (high) off-chip voltage to the cores which are then “voltage-stacked” to generate the near-threshold (low) voltages based on Kirchhoff’s voltage law through charge recycling. However, the effectiveness of this implicit down-conversion is affected by the current imbalance among the cores. The paper presents a design methodology and optimization strategy for highly efficient charge recycling on-chip regulation using a push-pull switched capacitor (SC) circuit. A dual-boundary hysteretic feedback control circuit has been designed for stacked loads. A stacked-voltage domain with its self-regulation capability combined with a SC converter has shown average efficiency of 78%–93% for 2:1 down-conversion with ILoad (max) of 200 mA and workload imbalance varying from 0–100%. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)

Journal Contact

MDPI AG
JLPEA Editorial Office
St. Alban-Anlage 66, 4052 Basel, Switzerland
jlpea@mdpi.com
Tel. +41 61 683 77 34
Fax: +41 61 302 89 18
Editorial Board
Contact Details Submit to JLPEA
Back to Top