Electronics

Research

13 pages, 4943 KiB

Open AccessArticle

Soft Error Simulation of Near-Threshold SRAM Design for Nanosatellite Applications

by Laurent Artola, Benjamin Ruard, Julien Forest and Guillaume Hubert

Electronics 2023, 12(18), 3968; https://doi.org/10.3390/electronics12183968 - 20 Sep 2023

Viewed by 944

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 [...] Read more.

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

13 pages, 10659 KiB

Open AccessArticle

Effect of Non-Ideal Cross-Sectional Shape on the Performance of Nanosheet-Based FETs

by Fengyu Kuang, Cong Li, Haokun Li, Hailong You and M. Jamal Deen

Electronics 2023, 12(16), 3419; https://doi.org/10.3390/electronics12163419 - 11 Aug 2023

Viewed by 1196

Abstract

In this article, the effects of non-ideal cross-sectional shapes of stacked nanosheet FET (NSFET) and nanosheet FET with inter-bridge channel (TreeFET) are studied through calibrated 3D TCAD simulations. The impact of non-ideal cross-sectional shapes on the electrical characteristics due to insufficient/excessive etch processes [...] Read more.

In this article, the effects of non-ideal cross-sectional shapes of stacked nanosheet FET (NSFET) and nanosheet FET with inter-bridge channel (TreeFET) are studied through calibrated 3D TCAD simulations. The impact of non-ideal cross-sectional shapes on the electrical characteristics due to insufficient/excessive etch processes are investigated in terms of inner spacer (IS), nanosheet (NS) channel, and inter-bridge (IB) channel. Simulation results show that the geometry and material of the IS have significant effects on the performance of the NSFET. Compared with the rectangular inner spacer (RIS), the low-k crescent inner spacer (CIS) enhances the gate control capability while the high-k CIS degrades the drain-induced barrier lowering (

D I B L

) and reduces the gate capacitance (

C_{g g}

). The tapered NS channel improves short-channel effects (SCEs), but sacrifices the driving current. For the TreeFET, considering the fin angle and concave arc, the IB channel can degrade the gate control capability, and SCEs degradation is severe compared to the ideal structure. Therefore, the non-ideal cross-sectional shapes have a significant impact on NSFET-based structure. This research provides development guidelines for process and structure optimization in advanced transistor technology nodes. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

12 pages, 9362 KiB

Open AccessArticle

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

by Donghan Ki, Minwoong Lee, Namho Lee and Seongik Cho

Electronics 2023, 12(15), 3331; https://doi.org/10.3390/electronics12153331 - 3 Aug 2023

Viewed by 1010

Abstract

This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, [...] Read more.

This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility. Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the TID effect was validated through experiments. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

10 pages, 2488 KiB

Open AccessArticle

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

by Pushpa Raikwal, Prashant Kumar, Meena Panchore, Pushpendra Dwivedi and Kanchan Cecil

Electronics 2023, 12(14), 3198; https://doi.org/10.3390/electronics12143198 - 24 Jul 2023

Viewed by 1035

Abstract

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the [...] Read more.

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

12 pages, 2750 KiB

Open AccessArticle

An Improved Structure Enabling Hole Erase Operation When Using an IGZO Channel in a 3D NAND Flash Structure to Which COP (Cell-On-Peri) Structure Is Applied

by Seonjun Choi, Myounggon Kang and Yun-Heub Song

Electronics 2023, 12(13), 2945; https://doi.org/10.3390/electronics12132945 - 4 Jul 2023

Cited by 2 | Viewed by 1586

Abstract

In this paper, we proposed an improved (Indum-Galum-Zinc-Oxide) IGZO-Filler (IF) structure that can be used in a Cell-On-Peri (COP) structure by improving the excellent erase performance of the IGZO-Pillar (IP) structure. The IP structure mentioned above is a structure that we announced in [...] Read more.

In this paper, we proposed an improved (Indum-Galum-Zinc-Oxide) IGZO-Filler (IF) structure that can be used in a Cell-On-Peri (COP) structure by improving the excellent erase performance of the IGZO-Pillar (IP) structure. The IP structure mentioned above is a structure that we announced in a previous study, and this structure overcomes the poor hole carrier characteristics of IGZO when the IGZO channel was used in the early 3D NAND Flash structure and enables hole erase operation. The proposed structure showed that, despite the very poor hole carrier characteristics of IGZO, hole erase operation is sufficiently possible even if only a few hole carriers exist in a thin pillar of 5 nm thickness. Simulation results show that the proposed structure exhibits a fast erase rate of 100 μs, similar to that of the existing structure, while maintaining the low leakage current properties inherent in the IGZO material. Therefore, the proposed structure is expected to maintain the excellent characteristics of the IGZO channel even in the 3D NAND Flash of the COP structure, which enables erasure operation while overcoming leakage current and temperature stability problems of existing polysilicon channels. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

14 pages, 7023 KiB

Open AccessArticle

Investigation of Electro-Thermal Performance for TreeFET from the Perspective of Structure Parameters

by Weijing Liu, Xinfu Pan, Jiangnan Liu and Qinghua Li

Electronics 2023, 12(7), 1529; https://doi.org/10.3390/electronics12071529 - 24 Mar 2023

Viewed by 1296

Abstract

In this work, the electro-thermal properties of TreeFET, which combines vertically stacked nanosheet (NS) and fin-shaped interbridge (IB) channels, are investigated in terms of interbridge width (W_IB), nanosheet space (S_NS) and nanosheet width (W_NS) by TCAD simulation. [...] Read more.

In this work, the electro-thermal properties of TreeFET, which combines vertically stacked nanosheet (NS) and fin-shaped interbridge (IB) channels, are investigated in terms of interbridge width (W_IB), nanosheet space (S_NS) and nanosheet width (W_NS) by TCAD simulation. Electrical characteristics such as electron density distributions, on/off-state current (I_ON, I_OFF), subthreshold swing (SS) and self-heating effects (SHE) such as lattice temperature and thermal resistance (R_th) are systematically studied to optimize the performance of TreeFET. The result shows that a smaller W_IB mitigates the short-channel effects and increases the electron concentration in NS channels but increases thermal resistance. A larger S_NS increases the on-state current while compensating for the gate drive loss and mitigating the thermal coupling effect between NS channels but results in longer conduction paths of carriers and heat, which hinders further improvements. Moreover, a suitable W_NS is required to lessen the decline of gate controllability induced by IB channels. Hence, suitable geometry parameters should be selected to achieve a compromise between thermal and electrical performance. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

9 pages, 1661 KiB

Open AccessArticle

Low-Frequency Noise Modeling of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistors

by Yuan Liu, Weijie Ye, Xiaoming Xiong and Wanling Deng

Electronics 2022, 11(19), 3050; https://doi.org/10.3390/electronics11193050 - 25 Sep 2022

Viewed by 1509

Abstract

4H-silicon carbide metal-oxide-semiconductor field-effect transistors (4H-SiC MOSFETs) show 1/f low-frequency noise behavior. In this paper, this can be explained by the combination of the mobility fluctuation (Δμ) and the carrier number fluctuation (ΔN) theories. The Δμ theory [...] Read more.

4H-silicon carbide metal-oxide-semiconductor field-effect transistors (4H-SiC MOSFETs) show 1/f low-frequency noise behavior. In this paper, this can be explained by the combination of the mobility fluctuation (Δμ) and the carrier number fluctuation (ΔN) theories. The Δμ theory believes that LFN is generated by the bulk defects, while the ΔN theory holds that LFN originates from the extraordinarily high oxide traps. For 4H-SiC MOSFETs, significant subthreshold noise will appear when only the ΔN theory attempts to model LFN in the subthreshold region. Therefore, we account for the high density of bulk defects (Δμ theory) and characterize the subthreshold noise. The theoretical model allows us to determine the bulk density of the trap states. The proposed LFN model is applicable to SiC MOSFETs and accurately describes the noise experimental data over a wide range of operation regions. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

7 pages, 3016 KiB

Open AccessArticle

L_g = 50 nm Gate-All-Around In_0.53Ga_0.47As Nanosheet MOSFETs with Regrown In_0.53Ga_0.47As Contacts

by In-Geun Lee, Hyeon-Bhin Jo, Ji-Min Baek, Sang-Tae Lee, Su-Min Choi, Hyo-Jin Kim, Wan-Soo Park, Ji-Hoon Yoo, Dae-Hong Ko, Tae-Woo Kim, Sang-Kuk Kim, Jae-Gyu Kim, Jacob Yun, Ted Kim, Jung-Hee Lee, Chan-Soo Shin, Jae-Hak Lee, Kwang-Seok Seo and Dae-Hyun Kim

Electronics 2022, 11(17), 2744; https://doi.org/10.3390/electronics11172744 - 31 Aug 2022

Viewed by 2393

Abstract

In this paper, we report the fabrication and characterization of L_g = 50 nm Gate-All-Around (GAA) In_0.53Ga_0.47As nanosheet (NS) metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-20 nm nanosheet thickness that were fabricated through an S/D regrowth process. The fabricated [...] Read more.

In this paper, we report the fabrication and characterization of L_g = 50 nm Gate-All-Around (GAA) In_0.53Ga_0.47As nanosheet (NS) metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-20 nm nanosheet thickness that were fabricated through an S/D regrowth process. The fabricated GAA In_0.53Ga_0.47As NS MOSFETs feature a bi-layer high-k dielectric layer of Al₂O₃/HfO₂, together with an ALD-grown TiN metal-gate in a cross-coupled manner. The device with L_g = 50 nm, W_NS = 200 nm and t_NS = 10 nm exhibited an excellent combination of subthreshold-swing behavior (S < 80 mV/dec.) and carrier transport properties (g_{m_max} = 1.86 mS/μm and I_ON = 0.4 mA/μm) at V_DS = 0.5 V. To the best of our knowledge, this is the first demonstration of In_xGa_1-xAs GAA NS MOSFETs that would be directly applicable for their use in future multi-bridged channel (MBC) devices. Full article

(This article belongs to the Special Issue Advanced CMOS Devices)

► Show Figures

Figure 1

Journal Menu

Journal Browser

Advanced CMOS Devices

Share This Special Issue

Special Issue Editor

Special Issue Information

Keywords

Published Papers (8 papers)

Research

Further Information

Guidelines

MDPI Initiatives

Follow MDPI