Special Issue "Selected Papers from IEEE S3S Conference 2014"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (20 February 2015)

Special Issue Editors

Guest Editor
Prof. David Bol

ICTEAM Institue, Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
Website | E-Mail
Phone: +3210472539
Fax: +32 10472598
Interests: ultra-low-power/ultra-low-voltage IC design; technology/circuit interaction; variability mitigation; compact modeling; design automation; innovative logic styles; advanced CMOS and post-CMOS technologies and green semiconductor manufacturing
Guest Editor
Dr. Steven A. Vitale

Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420-9108, USA
E-Mail
Fax: 1 781 981 7889

Special Issue Information

Dear Colleagues,

For more than two decades, low-power consumption has been paramount for integrated circuits (ICs) and systems-on-a-chip (SoCs). In today’s sub-100 nm technologies, low-power design flows are maturing with techniques, such as clock/power gating, multi-Vt/Vdd assignment, and dynamic frequency/voltage scaling, becoming mainstream. However, further power savings are still needed for extremely power-constrained applications, such as green computing, mobile wireless communications, sensor networks, and biomedical devices. Feasible ways of achieving further power savings include, for example, sub-threshold and ultra-low-voltage operation, SOI technology and circuits, and 3-D and heterogeneous integration. The 2014  IEEE Unified S3S (SOI-3D-SubVt) Conference event gathered researchers studying the aforementioned three topics to share their views and advances regarding lower-power and more efficient ICs and SoCs.

This issue of JLPEA is the fourth special issue dedicated to selected papers from the IEEE S3S Conference 2014 held in Millbrae, CA, on October 6-9, 2014. Extended versions of papers presented at the conference will be invited for submission to this special issue. A selection of the invited papers will be made based on their low-power content and their scientific/technical excellence.

Prof. David Bol
Steven A. Vitale
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

About Copyright

For the IEEE-copyrighted materials published in the S3S proceedings (e.g. figures/tables), the authors are responsible to acquire reprint permissions if they want to use them without significant modifications and to make the following IEEE credit/copyright notice appears prominently in the figure/table caption:
Based on "(full paper title)", by (authors' names) which appeared in (complete publication information). © [Year] IEEE.

Moreover, a new title is requested for the new paper (extended version of the IEEE conference paper), to indicate that the paper has been substantially revised.
Thank you very much!

Keywords

  • ultra-low voltage circuits and design techniques
  • SOI-specific circuits and design techniques
  • SOI devices, processes, and technologies
  • 3-D and heterogeneous system integration
  • memory design and technologies
  • analog and RF technologies and circuits
  • implantable and handheld biomedical devices
  • transistor variability and mitigation
  • ultra-low-power computation
  • device and fabrication technology
  • energy harvesting techniques
  • unattended remote sensors

Published Papers (6 papers)

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Research

Open AccessArticle A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories
J. Low Power Electron. Appl. 2015, 5(3), 165-182; doi:10.3390/jlpea5030165
Received: 3 March 2015 / Revised: 23 June 2015 / Accepted: 28 July 2015 / Published: 11 August 2015
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Abstract
This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level,
[...] Read more.
This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap) is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
Open AccessArticle A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities
J. Low Power Electron. Appl. 2015, 5(2), 130-150; doi:10.3390/jlpea5020130
Received: 1 April 2015 / Revised: 3 June 2015 / Accepted: 8 June 2015 / Published: 23 June 2015
Cited by 1 | PDF Full-text (3114 KB) | HTML Full-text | XML Full-text
Abstract
The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power
[...] Read more.
The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
Open AccessArticle Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates
J. Low Power Electron. Appl. 2015, 5(2), 116-129; doi:10.3390/jlpea5020116
Received: 20 February 2015 / Accepted: 20 May 2015 / Published: 25 May 2015
PDF Full-text (419 KB) | HTML Full-text | XML Full-text
Abstract
In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold
[...] Read more.
In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
Figures

Open AccessArticle Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits
J. Low Power Electron. Appl. 2015, 5(2), 101-115; doi:10.3390/jlpea5020101
Received: 23 February 2015 / Revised: 8 May 2015 / Accepted: 14 May 2015 / Published: 21 May 2015
Cited by 1 | PDF Full-text (4981 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge
[...] Read more.
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
Open AccessArticle Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View
J. Low Power Electron. Appl. 2015, 5(2), 69-80; doi:10.3390/jlpea5020069
Received: 19 February 2015 / Revised: 16 April 2015 / Accepted: 21 April 2015 / Published: 29 April 2015
Cited by 2 | PDF Full-text (305 KB) | HTML Full-text | XML Full-text
Abstract
This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG),
[...] Read more.
This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold voltage (VT), higher gm/ID ratio and higher |AV| due to the dynamically reduced threshold voltage and stronger transversal electric field. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
Open AccessArticle A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention
J. Low Power Electron. Appl. 2015, 5(2), 57-68; doi:10.3390/jlpea5020057
Received: 20 February 2015 / Revised: 8 April 2015 / Accepted: 10 April 2015 / Published: 17 April 2015
PDF Full-text (829 KB) | HTML Full-text | XML Full-text
Abstract
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two
[...] Read more.
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)

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