Special Issue "Selected Papers from IEEE ISOCC Conference 2016"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 June 2017)

Special Issue Editors

Guest Editor
Prof. Dr. Minsu Choi

Department of Electrical and Computer Engineering, Missouri University of Science and Technology, Rolla, MO 65409, USA
Website | E-Mail
Interests: low-power SoC (System-on-Chip) design; low-power asynchronous logic; low-power stochastic/approximate computing; security, trustworthiness and reliability of low-power circuits and systems; emerging technologies for low-power systems; parallel and scalable low-power computing; defect and fault-tolerance in low-power circuits and systems; low-power heterogeneous accelerators
Guest Editor
Prof. Dr. Yong-Bin Kim

Department of Electrical & Computer Engineering, Northeastern University, Boston, MA, USA
Website | E-Mail

Special Issue Information

Dear Colleagues,

Journal of Low Power Electronics and Applications (ISSN 2079-9268, http://www.mdpi.com/journal/jlpea) is an open access journal, which provides an advanced forum for the studies of electronics for low power applications. It publishes reviews, regular research papers and short communications. JLPEA’s aim is to encourage scientists to publish their experimental and theoretical results in as much detail as possible. There is no restriction on the length of the papers. The full experimental details must be provided so that the results can be reproduced.

This Special Issue of JLPEA is dedicated to selected papers from the 13th IEEE International SoC (System-on-Chip) Design Conference (ISOCC 2016) held in Jeju, Korea from 23–26 October, 2016. Extended versions of papers presented at the conference will be invited for submission to this Special Issue. A selection of the invited papers will be made based on their low-power relevance and their scientific/technical merit.

Prof. Minsu Choi
Prof. Yong-Bin Kim
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

About Copyright

For the IEEE-copyrighted materials published in the ISOCC proceedings (e.g. figures/tables), the authors are responsible to acquire reprint permissions if they want to use them without significant modifications and to make the following IEEE credit/copyright notice appears prominently in the figure/table caption:

Based on "(full paper title)", by (authors' names) which appeared in (complete publication information). © [Year] IEEE.

Moreover, a new title is requested for the new paper (extended version of the IEEE conference paper), to indicate that the paper has been substantially revised.

Keywords

  • Low-Power Analog/RF/Mixed-Signal Circuits: Analog Circuits/Data Converters/High-Speed Interface and Wireline Ics/Wireless and RF ICs
  • Power and Energy Circuits: Power Management Circuit/Energy Harvesting Circuits/Power and Energy Circuits and Systems
  • Low-Power Digital VLSI Circuits and Systems: Digital Integrated Circuits and VLSI Architectures/Memory Circuits and Systems/Multimedia Systems and Applications/Digital Signal Processing Systems and Applications/Circuits & Systems for Communications Processor, Embedded Systems and Software
  • Low-Power SoC Design Methodology: HW-SW Co-design/SoC Testing/Design Verification/Signal Integrity/Interconnect Modeling and Simulation
  • Low-Power Circuits and Systems for Emerging Technologies: Sensory Circuits and Systems/Biomedical Circuits and Systems/Automotive Circuits and Systems IoT/IoE Circuits and Systems.Nanoelectronics and Gigascale Circuits and Systems/3-D ICs and SoC Packages

Published Papers (2 papers)

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Research

Open AccessArticle Characterization of an ISFET with Built-in Calibration Registers through Segmented Eight-Bit Binary Search in Three-Point Algorithm Using FPGA
J. Low Power Electron. Appl. 2017, 7(3), 19; doi:10.3390/jlpea7030019
Received: 31 May 2017 / Revised: 10 July 2017 / Accepted: 11 July 2017 / Published: 13 July 2017
PDF Full-text (2598 KB) | HTML Full-text | XML Full-text
Abstract
Sensors play the most important role in observing changes in an environment they are a part. They detect even the smallest changes and send the information to other electronic devices. Making sure that these sensors provide an accurate output is equally crucial, as
[...] Read more.
Sensors play the most important role in observing changes in an environment they are a part. They detect even the smallest changes and send the information to other electronic devices. Making sure that these sensors provide an accurate output is equally crucial, as the data it measures and collects are used for analysis. Until now, calibrating sensors has been done manually by following a sequence of procedures, and is usually performed on-site or in a laboratory prior to deployment. To eliminate the manual procedure in the calibration (at the very least), an ion-sensitive field-effect transistor (ISFET) with a built-in calibration registers circuit was created through segmented eight-bit binary search in a three-point algorithm using a field-programmable gate array (FPGA). The circuit was created using a three-point calibration algorithm and three standard buffers (pH 4, pH 7, and pH 10). The block diagram, schematic diagram, and the number of logic gates were derived after synthesizing the Verilog program in Xilinx/FPGA. An average of 0.30% error was computed to prove the reliability of the created circuit using FPGA. Having an ISFET with built-in calibration registers will alleviate the work of experts in performing calibrations. This would follow the plug and play standard, hence its being a calibration-ready ISFET device. With this feature, it could be used as a pH level meter or a remote sensor node in several applications. Full article
(This article belongs to the Special Issue Selected Papers from IEEE ISOCC Conference 2016)
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Open AccessArticle High Performance Receiver Design for RX Carrier Aggregation
J. Low Power Electron. Appl. 2017, 7(2), 9; doi:10.3390/jlpea7020009
Received: 27 March 2017 / Revised: 26 April 2017 / Accepted: 27 April 2017 / Published: 1 May 2017
PDF Full-text (845 KB) | HTML Full-text | XML Full-text
Abstract
Carrier aggregation is one of the key features to increase the data rate given a scarce bandwidth spectrum. This paper describes the design of a high performance receiver suitable for carrier aggregation in LTE-Advanced and future 5 G standards. The proposed architecture is
[...] Read more.
Carrier aggregation is one of the key features to increase the data rate given a scarce bandwidth spectrum. This paper describes the design of a high performance receiver suitable for carrier aggregation in LTE-Advanced and future 5 G standards. The proposed architecture is versatile to support legacy mode (single carrier), inter-band carrier aggregation, and intra-band carrier aggregation. Performance with carrier-aggregation support is as good as legacy receivers. Contradicting requirements of high linearity and the low noise is satisfied with the single-gm receiver architecture in addition to supporting carrier aggregation. The proposed cascode-shutoff low-noise trans-conductance amplifier (LNTA) achieves 57.1 dB voltage gain, 1.76 dB NF (noise figure) , and - 6 . 7 dBm IIP3 (Third-order intercept point) with the power consumption of 21.3 mW in the intra-band carrier aggregation scenario. With legacy mode, the same receiver signal path achieves 56.6 dB voltage gain, 1.33 dB NF, and - 6 . 2 dBm IIP3 with a low power consumption of 7.4 mW. Full article
(This article belongs to the Special Issue Selected Papers from IEEE ISOCC Conference 2016)
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