Special Issue "Low Power Electronics - Recent Developments"

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (25 December 2011)

Special Issue Editor

Guest Editor
Prof. Dr. Orly Yadid-Pecht

Director, Integrated Sensors, Intelligent Systems (ISIS), Electrical Engineering Department, University of Calgary, Calgary AB T2N1N4, Canada
Website | E-Mail
Interests: CMOS image sensors; "smart" systems; hardware based image processing; micro-nano systems; bio-medical micro-systems

Special Issue Information

Dear Colleagues,

This Special Issue is seeking solid papers from authors who contributed papers in Low Power Electronics in recent high quality conferences. Expanded versions of recent conference papers are welcome, but only when significant details have been added. Both research articles and review articles are invited. The issue is scheduled for publication in March, 2012.

Prof. Dr. Orly Yadid-Pecht
Guest Editor

Published Papers (2 papers)

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Research

Open AccessArticle VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy
J. Low Power Electron. Appl. 2012, 2(2), 127-142; doi:10.3390/jlpea2020127
Received: 31 December 2011 / Revised: 22 March 2012 / Accepted: 26 March 2012 / Published: 29 March 2012
Cited by 7 | PDF Full-text (151 KB)
Abstract
A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading
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A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α† = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α† = 4.5958 for an 8% reduction in total power (PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy. Full article
(This article belongs to the Special Issue Low Power Electronics - Recent Developments)
Open AccessArticle Analysis of Dynamic Differential Swing Limited Logic for Low-Power Secure Applications
J. Low Power Electron. Appl. 2012, 2(1), 98-126; doi:10.3390/jlpea2010098
Received: 28 December 2011 / Revised: 2 March 2012 / Accepted: 2 March 2012 / Published: 16 March 2012
Cited by 3 | PDF Full-text (392 KB)
Abstract
Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A complete
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Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A complete analysis of an advanced encryption standard (AES) S-box is conducted using a low-power (LP) 65 nm CMOS technology node. Measurements show that the DDSLL S-box has 35% less power consumption than the static CMOS S-box, with an area increase of only 12%, at the expense of a 2.5× increase in delay which remains fairly acceptable for low-power applications such as RFIDs and smart cards. Also when compared to other dynamic differential logic (DDL) styles, simulation results show that DDSLL and dynamic current mode logic (DyCML) consume the same power which is about 1.8× less that of sense amplifier based logic (SABL). The effect of process variations is also studied, measurement results show that the DDSLL style has lower variability in terms of dynamic power as the activity factor (αF) is deterministic thanks to glitch-free operation. As for security, the perceived information metric demonstrates that the DDSLL S-box has a 3× security margin compared to static CMOS. Therefore, DDSLL presents an interesting tradeoff between improved security and area constrained low-power designs. Full article
(This article belongs to the Special Issue Low Power Electronics - Recent Developments)

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