Open AccessArticle
Design and Implementation of a Low-Power Biopotential Amplifier in 28 nm CMOS Technology with a Compact Die-Area of 2500 μm2 and an Ultra-High Input Impedance
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Esmaeil Ranjbar Koleibi, William Lemaire, Konin Koua, Maher Benhouria, Reza Bostani, Mahziar Serri Mazandarani, Luis-Philip Gauthier, Marwan Besrour, Jérémy Ménard, Mahdi Majdoub, Benoit Gosselin, Sébastien Roy and Réjean Fontaine
Sensors 2025, 25(7), 2320; https://doi.org/10.3390/s25072320 (registering DOI) - 5 Apr 2025
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Abstract
Neural signal recording demands compact, low-power, high-performance amplifiers, to enable large-scale, multi-channel electrode arrays. This work presents a bioamplifier optimized for action potential detection, designed using TSMC 28 nm HPC CMOS technology. The amplifier integrates an active low-pass filter, eliminating bulky DC-blocking capacitors
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Neural signal recording demands compact, low-power, high-performance amplifiers, to enable large-scale, multi-channel electrode arrays. This work presents a bioamplifier optimized for action potential detection, designed using TSMC 28 nm HPC CMOS technology. The amplifier integrates an active low-pass filter, eliminating bulky DC-blocking capacitors and significantly reducing the size and power consumption. It achieved a high input impedance of 105.5 GΩ, ensuring minimal signal attenuation. Simulation and measurement results demonstrated a mid-band gain of 58 dB, a −3 dB bandwidth of 7 kHz, and an input-referred noise of 11.1 μ
, corresponding to a noise efficiency factor (NEF) of 8.4. The design occupies a compact area of 2500 μ
, making it smaller than previous implementations for similar applications. Additionally, it operates with an ultra-low power consumption of 3.4 μW from a 1.2 V supply, yielding a power efficiency factor (PEF) of 85 and an area efficiency factor of 0.21. These features make the proposed amplifier well suited for multi-site in-skull neural recording systems, addressing critical constraints regarding miniaturization and power efficiency.
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