Comparison of Fitting Current–Voltage Characteristics Curves of FinFET Transistors with Various Fixed Parameters

Abstract

In the deep submicron regime, FinFET successfully suppresses the leakage current using a 3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate is applied with a bias wholly wrapping the channel. Fortunately, a scanning photo-lithography using extensive ultraviolet (EUV) and multi-mask task carefully resolves critical dimension issues. The ensuing anisotropic plasma dry etching is somehow a subsequent challenging process, which consumes the edge of original ‘I’-shape epitaxial silicon and causes dimension loss, and thus produces fin-like bodies as prepared channels. In order to protect the transistors from malfunction due to dimension over-etching, fin width is taken to be 120 nanometers, while the channel lengths vary. The prepared transistors are measured and characteristic curves are fitted for analysis. Measured current versus voltage characteristic curves are fitted with three parameters (transistor geometry constant, threshold voltage, and Early voltage) in the conventional current-voltage formula, which are allowed to vary as the short channel effects or process-related issues are taken into account. In this paper, one of the three is deliberately set to be fixed for a transistor, and the others are freely chosen and determined to reach minimum variation. Various conclusions through comparisons and analysis may give important feasible applications in the future.

1. Introduction

Reliable processes have been used to manufacture MOSFET transistors, which are followed by FinFET for chasing speed. The structure from planar to 3D is appreciated owing to controllability because of exceptionally leaky current of the short channel effect. There are several other ways to improve the speed of integrated circuit (IC), especially by enhancing the performances of transistors. The value k_n is proportional to the product of mobility and capacitance per m², and the current appears to be increased by promoting either the mobility of carriers or the di-electric constant of the capacitor. The mobility of carriers may be higher if the silicon channel is replaced with Ge whose mobility is from 2.5 to 4.0 times that of epi-silicon. In addition, the di-electric constant of tantalum oxide mixed with Hf is approximately 25 to 27, which is approximately five times that of conventional nitrided silicon di-oxide. The advanced techniques mentioned above can be used to enhance FinFET devices, making them even more promising [1,2,3,4,5,6,7,8,9,10,11].

Nevertheless, there still exist some limitations, e.g., heat dissipation. As electrical signals or power flow, Ohm’s heat inevitably increases as the size shrinks. The temperature may soar up, and electrical performances of a single transistor may simply degrade unless heat sink is found and the heat dissipation gets resolved. GAA (gate-all-around) MOSFET thus provides a possible solution using Al₂O₃ as an insulator compared with HfO₂ and SiO₂ [12].

To realize characteristics of a transistor or even to design an integrated circuit, a useful model (I–V formula) has to be proposed. More than fifty years ago, the conventional formula for describing electrical characteristics of transistors was introduced. However, fitting may not be possible for potential analysis unless certain modification are implemented, as presented in Equations (1) and (2) [7,8]. In the model, three basic primary parameters (k_N, V_th, and λ) are presented even though the model has been progressively modified many times by using equivalent circuits. However, in a sense, the conventional formula has been evolving, making many contributions in the past. Therefore, the modified basic model in Equations (1) and (2) is preferred here; model-fitting is carried out for analysis as well as used to examine the transistor.

On the one hand, K_n values linked to the sizes are considered to be proportional to channel width and inversely proportional to channel length. On the other hand, the threshold voltage is linearly dependent on the depth of depletion region as gate bias is applied to the gate, which may be related to process-induced dimension loss. Furthermore, short channel effects and the so-called Early voltage (1/λ) may be responsible for the corresponding leakage current. Three parameters mentioned in the I-V formula can be deliberately chosen to be separately fixed, and the minimum total deviation in Equation (3) is utilized to compare and provide important information [10,11,12,13,14,15,16,17,18,19].

In this paper, we consider only FinFET transistors with 0.120 micron-wide fins, whose channel lengths may be 100, 160, or 240 nanometers (W120L100, W120L160, or W120L240). Those are measured, fitted, analyzed, and compared. Some physical implications may then be concluded.

2. Preparation and Measurements

2.1. Preparation

Epi-silicon is layer-grown, followed by ionic dry etching, and is required for its purity and resulting electrical performance. There are many three-dimensional “I” shapes with two ends as source and drain after dry etching. Only 120 nm-wide slim fins between source and drain are considered in this paper from a dimension-loss point of view. Each channel with an aspect ratio 1:9 gives an equivalent total channel width that is 19 = 1 + 9 + 9 times that of the 120 nm-wide fin. An ultra-thin gate oxide—gate oxide that is chemically vapor-deposited with a layer of heavily arsenic-doped poly-silicon—is grown on the surface of the fin channel and used as the gate.

2.2. Fitting I_DS–V_DS and I_DS–V_GS

FinFET transistors which are similar to MOSFET have two-regime modified electrical characteristics as expressed in the following:

$$I_{DS}(Triode)=k_N[(V_{GS}-V_{th})V_{DS}-V_{DS}{}^2/2](1+\lambda V_{DS})$$

(1)

$$\begin{gathered} I_{DS}(Saturation)=\frac{k_N}{2}{(V_{GS}-V_{th})}^2(1+\lambda V_{DS})\hspace{1em}\hspace{1em} \\ \begin{array}{l}\mathit{where} k_N=\frac{C_{ox}{}^{(1)}{W}_{eff}\mu }{L_o},\hspace{1em}{V}_{th}{}^{} \mathit{is} \mathit{threshold} \mathit{voltage},\\ \mathit{and}\hspace{1em}\lambda =\frac{1}{\left|V_A\right|}, \mathit{and} \alpha (\mathit{gate} \mathit{leakage} \mathit{coefficient}).\end{array} \end{gathered}$$

(2)

For conveniences in this paper, k_N can be written as Kn, and V_th can be also written as Vth. Also, C_ox⁽¹⁾ means gate oxide capacitance per m², V_A represents Early voltage, and W_eff = 19 W_o.

V_DS must be less than (V_GS − V_th) in Equation (1), while V_DS must be greater than (V_GS − V_th) in Equation (2). The parameters, Kn, Vth, and λ, are always determined to minimize the following deviation (δ) in Equation (3):

$$\delta ={\displaystyle \sum _{i=1}^N{(I_{fitting}-I_{measured})}_i{}^2}$$

(3)

3. Analysis and Discussion

The minimum deviation (δ) in Equation (3) is an achievable way for determining feasible parameters. The minimum requirement gives the best fit. There are three ways to test the goodness-of-fit for each transistor with different channel lengths and channel widths. One way is to fix Kn. Kn fixed at a certain value may help to find different corresponding values of Vth and λ at different values of V_G (0.25 V, 0.5 V, 0.75 V, and 1.0 V) by the minimum requirement in Equation (3). All the minimum values at V_G = 0.25 V, 0.5 V, 0.75 V, and 1.0 V are summed over and give a final total minimum deviation at the specific fixed Kn. Different final total minimum deviations are compared as shown in Figure 1a for the transistor denoted by W120L100. The least minimum deviation determines the final Kn of the respective transistor. All the Kn values are collected and listed in

Table 1. Three ways to collect fixed parameters of various transistors.

Gate Sizes	Kn(A/V2)	λ(1/V)	Vth(V)
W120L100	1.56 × 10−4	0.305	−0.250
W120L160	1.36 × 10−4	0.170	−0.150
W120L240	1.13 × 10−4	0.130	−0.025

[14,15,16,17,18,19,20,21,22].

The second way is to fix Vth. Vth fixed at a certain value may help to find different corresponding Kn and λ values at different values of V_G = 0.25 V, 0.5 V, 0.75 V, and 1.0 V by the minimum requirement in Equation (3). All the minimum values at V_G = 0.25 V, 0.5 V, 0.75 V, and 1.0 V are summed over and give a final total minimum deviation at the specific fixed Vth. Different final total minimum deviations are compared as shown in Figure 1b for the transistor denoted by W120L100. The least minimum deviation determines the final Vth of the respective transistor. All the Vth values are collected and listed in Table 1.

The third way is to fix λ. The λ fixed at a certain value may help to find different corresponding Kn and Vth values at different values of V_G = 0.25 V, 0.5 V, 0.75 V, and 1.0 V by the minimum requirement in Equation (3). All the minimum values at V_G = 0.25 V, 0.5 V, 0.75 V, and 1.0 V are summed over and give a final total minimum deviation at the specific fixed λ. Different final total minimum deviations are compared as shown in Figure 1c for the transistor denoted by W120L100. The least minimum deviation determines the final λ of the respective transistor. All the λ values are collected and listed in Table 1.

As shown in Figure 1a–c, the transistor W120L100 has the final fixed Kn = 1.56 × 10^{−4 A/V2}, the final fixed λ = 0.305 (1/V), and the final fixed Vth = −0.25 V. In addition, the corresponding total minimum deviations are 6.25 × 10^{−10 A2}, 1.27 × 10⁻¹¹ A², and 2.38 × 10⁻¹⁰ A², respectively. The value λ = 0.305 and the final minimum deviation 1.27 × 10⁻¹¹ A² has the final minimum deviation as compared with the other two ways of parameter-fixing.

As shown in Figure 2a–c, the transistor W120L160 has the final Kn = 1.36 × 10⁻⁴ A/V2, λ = 0.170 (1/V), and Vth = −0.150 V. In addition, the corresponding minimum deviations are 8.82 × 10⁻¹⁰ A², 2.14 × 10⁻¹⁰ A², and 1.83 × 10⁻¹⁰ A², respectively. The value Vth = −0.150 V and the final minimum deviation 1.83 × 10⁻¹⁰ A² has the final minimum deviation as compared with the other two ways of parameter-fixing.

As shown in Figure 3a–c, the transistor W120L240 has the final Kn = 1.13 × 10⁻⁴ A/V², λ = 0.130 (1/V), and Vth = −0.025 V. In addition, the corresponding minimum deviations are 3.70 × 10⁻¹¹ A², 2.95 × 10⁻¹¹ A², and 3.56 × 10⁻¹¹ A², respectively. The value λ = 0.130 and the final minimum deviation 2.95 × 10⁻¹¹ A² has the final minimum deviation as compared with the other two ways of parameter-fixing.

One intriguing observation is concerning negative Vth values. As shown in Figure 4a, Vth values plotted against channel length, surprisingly, is seen to be linear and the slope is determined to be 1.6071 (Volt/micron), as presented in Equation (4).

$$Vth=Vt{h}_O+1.6071L$$

(4)

$$\begin{array}{l}where\\ Vt{h}_O=-0.41071(Volt)\end{array}$$

This raises an interesting point: what if the channel length becomes larger, such as 500 nm which is 0.5 micron? The threshold voltage is found to be 0.25 by using conventional interpolation methods, as found in Figure 5b,c thus showing the channel-length-dependent line, which is encouraging and persuasive.

4. Conclusions

The fitting capability here became possible only when the conventional I-V characteristic formulas were modified in the triode region [7,8,17,19]. Even so, some confusingly ambiguous results arose, such as the associated size and process-related issues, thus the suggestion that only transistors with fin width W = 0.120 microns are taken into account [20]. Therefore, the three width splits including 0.120 microns, 0.115 microns, and 0.110 microns were examined in detail and produced the conclusion that only availability of W = 0.120 microns is fully supported [23]. One of the three parameters (Kn, Vth, and lambda) is individually fixed and the other two are tuned to find the corresponding minimum deviations as collected in Table 1 and

Table 2. Collected minimum deviations corresponding to three ways of fixing parameters.

Gate Sizes	Fixed Kn(A/V2)	Fixed λ(1/V)	Fixed Vth(V)
W120L100	6.25 × 10−11	1.27 × 10−11	2.38 × 10−10
W120L160	8.82 × 10−11	2.14 × 10−10	1.83 × 10−10
W120L240	3.70 × 10−11	2.95 × 10−11	3.56 × 10−11

, followed by three conclusive results as follows:

For fixed Kn, three respective Kn values of the three transistors with the most minimum deviations are found to be linear against the inverse of channel lengths, as shown in Figure 4a; additionally, the thickness of strong inversion layer in the channels is able to be calcu-lated and determined to be 203 angstroms [23].

For fixed lambda, three respective lambdas of the three transistors with the most minimum deviations determine the corresponding Early voltage values, which are plotted linearly against the inverse of channel lengths, as shown in Figure 4b. That characterizes the channel-length-dependent leakage current, i.e., the shorter the channel length, the leakier the transistor across source and drain. This Early-voltage-related leakage current may get larger, which is not expected as the channel length gets shorter.

For fixed Vth, three respective Vth values of the three transistors with the most minimum deviations are plotted linearly against channel lengths (100 nm, 160 nm, and 240 nm) in Figure 5a, which include another transistor whose channel length is 500 nm with a 120 nm wide fin to determine whether the tendency is still true. The measured I_DS–V_GS curve suggests 0.25 Volts threshold voltage, as presented in Figure 5c. Negative Vth values for shorter channel length in NFinFET may be interpreted as pro-cess-related size issues addressing dry-etching consuming processes since the thresh-old voltage depends on space charge in the depletion region [23]. That means Vth may b as low as −0.4 Volts as channel length approaches 10 nanometer scales, which may lead to extra current beyond the control.

The modified current–voltage formula used for fitting I–V characteristic curves is quite encouraging and remarkable. The fitting capability help give some underlying physical interpretations, which, unfortunately, set up a limitation for how far FinFET can go. In addition, FinFET also suffers from generated heat, and thus, down-graded performance and reliability issues. Therefore, effective heat dissipation substantially needs to be stressed. By applying bias-induced depletion techniques, GAA and Nanosheet FET may be alternative approaches in the future.