Innovative EMD-Based Technique for Preventing Coffee Grinder Damage from Stones with FPGA Implementation

Abstract

Coffee is one of the most widely consumed beverages globally, with Americans averaging 3.1 cups per day. However, before coffee beans can be brewed into a drinkable form, they undergo several critical stages, including harvesting, processing, roasting, grinding, and extraction. During the processing and roasting phases, a significant challenge arises: stones that are similar in size and shape to coffee beans can inadvertently mix into the batch. These stones are difficult to detect using conventional methods, and their presence can have severe consequences. When stones are ground alongside coffee beans, they can cause significant damage to the grinder’s burrs. Commercial coffee grinders typically employ conical or flat burrs, which consist of two circular discs or an inner blade and a disc. These burrs undergo specialized heat treatment and surface processing to ensure durability and precision, making them highly expensive components. Replacing damaged burrs is not only costly but also requires meticulous calibration of the parallelism between the inner blade and the disc to maintain grinding quality. The introduction of stones into the grinding process can lead to equipment damage, resulting in operational downtime and financial losses. To address this issue, this paper proposes a novel method based on Empirical Mode Decomposition (EMD) for detecting stones in coffee beans. The approach analyzes the acoustic wave patterns generated when stones impact or rotate within the grinder.

1. Introduction

Coffee is an especially important beverage in daily life. For many individuals who need to wake up early or work late into the night, their good working state relies heavily on coffee. As a result, the global coffee industry has grown significantly, with the commercial coffee shop market alone valued at $245.2 billion in 2024 and projected to grow annually by 4.51%. The rapid development of highly automated coffee machines has allowed coffee shops to meet high customer demands during peak hours. However, the production of coffee beans involves complex processes. After harvesting, coffee beans are sent to processing facilities where complex reactions involving the sugars, pectins, and various aromatic substances in the coffee cherries occur, fully infusing the coffee beans and imparting different flavors. During this process, foreign materials like small stones often remain mixed with the beans. These stones, resembling coffee beans in size and shape, pose challenges for detection and removal. Although multiple screening steps are typically employed in the subsequent stages of producing finished coffee beans, it remains difficult to eliminate stones from the coffee beans supplied to the market. For coffee production, stones that are not removed during the production process of finished coffee beans pose a significant problem. These stones are similar in color and shape to coffee beans or are mixed among the coffee grounds, making them hard to detect [1]. When these stones are mistakenly placed into the coffee grinder during the coffee production process, they can damage the grinder’s most expensive burrs [2]. Professional grinder has a complex procedure of burr alignment and parallelism calibration while replacing the burr [3,4]. In highly automated commercial settings that strive for efficiency, if such a problem occurs during peak hours, waiting to replace the burrs can result in substantial operational losses. Additionally, there are concerns about whether stones or metal fragments mixed into the coffee grounds due to burr damage might pose health risks. Currently, most research on this issue focuses on improving screening processes and introducing more advanced automated screening and classification methods during the production of finished coffee beans. These methods are primarily implemented using computer vision, machine learning, spectral analysis, or energy excitation techniques [5,6,7,8,9,10]. They offer good accuracy and efficiency for production line implementation. However, since these studies have primarily focused on improving coffee bean screening during production, these techniques offer high accuracy and efficiency, but their implementation is largely limited to large-scale production lines due to spatial and cost constraints, making them unsuitable for commercial coffee grinders. Alternatively, introducing such methods might necessitate additional structural designs, which could lead to inconvenience. This paper designs a process to detect whether stones are mixed into coffee beans when they are placed into the coffee machine and during the operation of the coffee machine, addressing the impact of stones not removed during the production process on coffee output. The process uses a microphone to capture the sound produced by the coffee grinder and employs Empirical Mode Decomposition (EMD) to extract features that can identify stones mixed into the coffee beans. The following points summarize the uniqueness and innovation of this study:

• Developed a method based on the Empirical Mode Decomposition (EMD) algorithm to detect the presence of stones mixed into coffee beans during the operation of coffee machines, along with a detection process to prevent collisions between coffee beans and the rotating burrs;
• Designed an efficient real-time FPGA implementation for the aforementioned detection method;
• Optimized the EMD extraction module through reuse, achieving resource consumption optimization by slightly increasing the processing delay per detection while minimally impacting data throughput, thereby facilitating its application on smaller FPGA or CPLD devices.

2. Materials and Methods

2.1. Overview: Overall Project Block Diagram

Figure 1 shows the system framework diagram of this method. delineating the three different modules of the project: sensor data acquisition, anomaly detection before operation, and anomaly detection during operation.

When coffee beans are placed into the grinder, the ADC collects sound from a microphone at a sampling rate of 48 kHz. If stones are introduced early, when the stones collide with the blades or burrs, strong high-frequency components will be generated around 12 kHz, as shown in Figure 2. The signal passes through a sixth-order bandpass IIR filter with a center frequency of 12 kHz and a bandwidth of 300 Hz, and the signal amplitude is compared to a preset threshold. If it exceeds the threshold, it indicates stone contamination.

If no fault is indicated in this step, the grinder starts rotating at the set speed, and the ADC collects 16-bit audio signals at the set sampling rate, sending them to an EMD circular buffer for processing. When the data sequence begins to be added into the EMD module, the local maxima and minima of the sequence are first searched and stored. The upper and lower envelopes are obtained by interpolating the local maxima and minima, and their average is calculated to produce the local mean sequence. This sequence is considered the residue of the current iteration and serves as the input for the next iteration. The result of subtracting this sequence from the original input becomes the IMF of the current iteration. This process repeats until the desired IMF7 is obtained. After obtaining the desired IMF7, the result undergoes FFT, resampling, and normalization, and the degree of deviation from the features during normal operation is measured using relative Shannon entropy. If the deviation is too large, a fault warning is issued. Using linear interpolation instead of cubic spline interpolation (CSI) can significantly reduce computational load but increases the noise across the full frequency band, thus affecting detection accuracy [11]. However, after applying a moving average (MA) filter to the linearly interpolated results, there is no significant difference compared to the results obtained with cubic splines, except for the presence of noticeable low-frequency mode mixing. After IMF7, the sampling rate should be reduced to 125 Hz, and the bandwidth is limited to approximately 60 Hz. Subsequently, a 64-point Fast Fourier Transform (FFT) is performed to analyze the frequency characteristics of IMF7. After FFT, the DC component affected by low-frequency mode mixing and the highest frequency component containing less information are discarded. The remaining results are resampled to 20 points, and Shannon entropy and relative entropy are calculated after energy normalization and compared to preset thresholds to determine stone contamination. During grinder operation, this process is continuously repeated.

2.2. Reasons for Using EMD Algorithm

EMD can be used to detect fault signals generated when stones are mixed into coffee beans. The grinder grinds coffee beans by rotating blades and burrs. When faulty components such as stones participate, the interactions between components produce different vibration patterns and transient features. EMD is a method that decomposes a complex signal sequence into Intrinsic Mode Functions (IMFs) and residuals [12]. Each decomposed IMF can characterize a certain periodic and stationary mode of the fault, making it easier for signal processing techniques such as Fourier Transform and cross-correlation to capture the desired information. When a fault occurs, the IMFs often contain signals that characterize the fault model [13,14]. The residual also contains transient features that may be excited by the fault [15]. By analyzing the IMFs and residuals, features that reveal whether the grinder is operating normally can be identified. Another advantage of EMD is its adaptability. Unlike wavelet transform-based or autoregressive methods, EMD does not require preset basis functions and can handle non-stationary signals [16], nor does EMD require noise whitening before decomposition [17]. This makes EMD highly suitable for analyzing fault signals in complex mechanical systems [18]. Fault signals in complex mechanical systems are often significantly weaker than the inherent modes of the system during normal operation and tend to undergo intermodulation with the system’s inherent modes [19]. EMD can remove the influence of these strong inherent modes, thereby better separating the desired fault modes and transient features [20].

2.3. Advantages of the FPGA Platform

For real-time detection embedded systems, low computational latency and computational overhead are important factors. FPGA (Field-Programmable Gate Array) demonstrates significant advantages due to its unique architecture and flexibility [21]. FPGA is a highly flexible integrated circuit that allows users to configure its logic functions through programming after manufacturing, thereby meeting specific application requirements [22,23]. Unlike traditional fixed-function chips, FPGAs consist of numerous programmable logic units, programmable interconnect networks, and input/output modules, enabling customization and optimization based on different application scenarios [24,25]. The programmable logic units within FPGAs consist of Look-Up Tables (LUTs), Flip-Flops, and other basic logic elements, capable of performing complex logic operations and data processing. By configuring these logic units, developers can design various digital circuits such as adders, multipliers, and state machines. These logic resources are typically designed using hardware description languages (e.g., Verilog). Developers write code that describes the circuit’s functions, mapping the logic functions onto the FPGA’s hardware resources. Synthesis tools convert this code into a netlist and, with other design constraints, generate a bitstream file that can be loaded onto the FPGA, implementing the required hardware circuit. FPGAs can achieve highly parallel computation, meaning multiple tasks can be executed simultaneously, significantly reducing overall computational latency [26,27]. This is particularly important for applications requiring immediate responses, such as fault detection. Additionally, the programmability of FPGAs allows for customization and optimization based on specific needs, ensuring maximum resource utilization and reducing computational overhead.

3. Design and Development

3.1. The Specific Method of the Implementation

Figure 3 shows the corresponding IMFs and the frequency characteristics of IMF7 for a grinder operating without faults, a grinder operating with coffee beans mixed with stones similar in appearance to coffee beans, and a grinder operating with coffee beans mixed with a certain number of gravel particles.

Due to the lack of power tools, the testing was conducted manually at approximately 100 rpm on a Helor 106 coffee grinder, as shown in Figure 4. Although there is significant interference due to human factors, this method remains feasible.

The measurements were made using an IEPE microphone B&K TYPE4958A, which has better low-frequency uncertainty and background noise, commonly used in high-end electronic equipment production lines due to microphone calibration. The impact of using microphones with worse low-frequency uncertainty and higher background noise on sound signal sensing in this method requires further study. From the frequency spectrum of IMF7 on the right side of Figure 2, whether a single stone similar in appearance to coffee beans or multiple small gravel pieces are present, additional spikes are excited in the originally flat frequency band. Therefore, when grinding coffee beans mixed with stones, the Shannon entropy value of IMF7 in the frequency domain significantly deviates from the Shannon entropy during normal operation [28]. By determining whether the relative entropy exceeds a given range, it can be determined whether the coffee beans in the grinder are abnormally mixed with stones during operation.

3.2. The FPGA Implementation Detail

The FPGA implementation specifically uses the Xilinx XCZU15EG evaluation board, with hardware synthesis developed and implemented on the Vivado HLS platform. Since the proposed IIR filter parameters are difficult to complete within the input range allowed by fixed-point arithmetic using FPGA’s on-chip DSP slices and since implementing floating-point arithmetic on the FPGA incurs significant hardware overhead [29,30], this part can be processed in real-time on the ESP32 MCU; therefore, the FPGA implementation does not include this section. The specific framework diagram of the FPGA implementation is shown in Figure 5.

The module for extracting IMFs on the FPGA refers to references [31], as shown in Figure 6.

The traditional method of envelope extraction through CSI interpolation at extreme points is difficult and resource-intensive with high computational latency. Using linear interpolation plus a moving average filter can achieve similar accuracy while effectively solving this problem. Simulations of this method revealed a significant issue with low-frequency mode mixing, but in the application of detecting stones mixed into coffee beans, even without using the DC component, the final result remains unaffected, and ideally, IMFs should not contain DC components. From the IMFs and frequency spectra shown in Figure 2, it can be observed that the high-frequency components of each iteratively decomposed IMF gradually decrease, while IMF7 primarily contains information concentrated within a 60 Hz bandwidth.

Therefore, directly downsampling the residual before inputting it into the next level [32], to half the original frequency rate; downsampling was attempted using both mean filtering and IIR filtering for signal preprocessing, but simulations did not show a better correlation in the frequency spectrum. Thus, it was decided not to perform signal preprocessing and to implement downsampling directly through extraction. Because the sampling rate of IMF7 output must ensure approximately a 60 Hz bandwidth, the signal’s sampling rate should not be lower than 8 kHz to ensure the required IMFs can be correctly decomposed. Simulations of the mean squared error under different sampling rates, using 48 kHz as a reference, showed that for all sampling rates not lower than 8 kHz, the mean squared error of different results was less than 0.025, indicating that the impact of the sampling rate on false positives under normal conditions is negligible.

Therefore, the sampling rate was selected as 8 kHz. In simulations of actual measurement samples, when the number of samples within the 60 Hz band after FFT reaches 20, a significant result can be obtained when a fault mode occurs. Therefore, after performing a 64-point FFT using Vivado FFT IP and discarding the DC and highest frequency components, the remaining 30 sample points are resampled to 20 sample points using linear interpolation for further processing. For the final downsampling to a sampling rate of 125 Hz, this introduces approximately a 0.5 s dead time after data begin to be input. Alternative steps, such as using a 32-point FFT interpolated to the same number of points or directly using 15 points after removing the DC component, were attempted to achieve shorter dead times, but these introduced more significant uncertainties in the result, thereby reducing the accuracy of small gravel detection. Therefore, a longer dead time with a 64-point FFT was chosen.

After completing the FFT, energy normalization calculation and modulus operations are critical steps [33,34]. To efficiently perform these calculations, the CORDIC (Coordinate Rotation Digital Computer) algorithm was employed. CORDIC is an iterative rotation-based algorithm that can perform square root and magnitude calculations without the need for multipliers, using a series of additions and shift operations [35,36]. In this system, the modulus calculation uses circular rotation mode. The adjustable precision feature of the CORDIC algorithm allows flexible configuration based on different application scenarios, further optimizing the overall system performance. In the FFT results, whichever of the real or imaginary parts has a larger absolute value is taken as the X input after taking the absolute value, thereby skipping the first iteration of CORDIC. The modulus calculation using CORDIC performs a total of 2–4 steps, totaling three iterations. After completing the iterations, the data are multiplied by the CORDIC scaling factor and sent to the buffer.

The entire process from input data to buffer write is carried out in a pipelined manner, fully leveraging the parallel processing capabilities of the FPGA to ensure computational real-time performance and high efficiency. The energy normalization calculation part uses two DSPs to calculate the cumulative energy of the resampled FFT results, allowing the use of more bits for calculations to ensure precision. After all outputs are accumulated, a hyperbolic rotation mode CORDIC performs the square root operation. The CORDIC relies on the previously used DSPs to iterate four times, followed by multiplication with a scaling factor that includes the reciprocal of the CORDIC gain and the reciprocal of the reference signal energy square root, to obtain the energy normalization result. After completing the energy normalization, the logarithm of the energy is calculated, followed by calculating the relative entropy with a preset value and scaling the final result again using the ratio of sampled energy to preset energy before comparing it to a preset threshold to obtain the judgment result. For division operations and logarithmic computations involved in the system, since these operations typically consume significant resources and have high computational latency in hardware implementations, this paper opts to use a lookup table (LUT) method.

This method precomputes and stores commonly used division and logarithmic values, allowing rapid retrieval of results through table lookup when needed, thereby significantly reducing computational latency [37,38]. Specifically, for division operations, the lookup table is designed based on the range and precision requirements of the dividend, storing the reciprocal of the dividend in discrete form to allow approximate division values to be obtained directly through multiplication during actual computations. Similarly, for logarithmic operations, the method maps the fractional part of the input signal to precomputed logarithmic value tables. This lookup method not only reduces hardware resource consumption but also improves computation speed, ensuring system efficiency in real-time signal processing.

The pipelined architecture was applied in the overall system design to further enhance computational efficiency and reduce latency [39,40]. Pipeline architecture breaks down complex computational tasks into multiple subtasks processed in parallel stages, achieving multi-level parallel computation. By breaking down a single complex combinational logic into simpler combinational logic handled in multiple stages and applying pipeline processing, data processing within a single clock cycle can be performed with lower latency, allowing the system to operate at higher clock frequencies [41,42]. This is achieved at the cost of increased overall processing delay and resource consumption, thereby significantly improving maximum throughput. In this fault detection module, pipeline application is reflected in the parallel processing of multiple computational steps, such as data acquisition, preprocessing, FFT computation, energy normalization, logarithmic computation, and result determination. This design not only increases system throughput but also reduces the waiting time between each computational step. Additionally, the pipelined structure helps reduce the impact of endpoint effects, i.e., errors that may be introduced due to improper handling of data block boundaries during signal processing. By processing each computational step in staged processing, the pipeline can smoothly transition between data blocks, ensuring the overall stability and accuracy of the computational results. Compared to the ESP32 implementation at 240 MHz with a 20.60-millisecond delay, this method achieves a minimum delay of approximately 0.002 milliseconds at a 200 MHz frequency, sufficient to update the judgment result once each sample is generated and meeting the conditions for extracting each level of IMFs.

For the simulation samples, the proposed method yielded a SNR of 13.93 dB for IMF7, with a variance-normalized MSE of 0.0358, a variance-normalized RMSE of 0.1891, and a correlation efficiency of 98.29%.

3.3. Innovation and Improvements in Module Reuse

From the methods, it is evident that, due to the downsampling design, the load on each IMF processing stage in the pipeline decreases progressively. The total load of the IMF modules from the second to the seventh stage is even less than that of the first IMF module, resulting in unnecessary waste of logic resources. To address this, module reuse can be employed to fully utilize the idle processing capacity of the modules [43,44]. Module reuse in a pipeline is not typically considered a wise design choice, as ensuring that each stage of the pipeline is correctly processed requires adding many registers to store the state and data of each stage, making it difficult to reduce logic resource consumption as expected [45,46]. Additionally, introducing more complex logic during this process can lower the maximum allowable clock frequency [47], and the clock cycles required to process each data unit may be significantly higher than ideal. Moreover, due to the difficulty in modular design for reused parts, this approach has poorer maintainability and scalability. However, because the current design requires processing data at extremely low rates and is not as sensitive to the increased delay and reduced clock frequency, and because the IMF modules have significantly unbalanced loads, the approach is discussed and designed in this paper. As shown in Figure 7, module reuse employs a clock divider to obtain divided clock signals at 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 times the clock frequency and uses these divided clock signals to select the current IMF stage being processed to balance the load. The selection signals correspond to BRAM and state registers, and data register addresses, to match the IMF extraction stages.

The divided clock signals generate an idle clock every 128th clock cycle, which ideally could be used to determine whether each pipeline stage has data to be processed and to more reasonably reinitialize the position of the clock divider to reduce possible maximum delay. However, in practice, it is difficult to correctly handle this process without lowering the clock frequency, so this design was not implemented in this paper. The selection signals generated by the divider are delayed through a series of delays and distributed to the IMF extraction and BRAM read phases to ensure pipeline efficiency. Since the envelope extraction through interpolation causes blocking, the subsequent moving average filter and local mean calculation are treated as the beginning of the pipeline. Each subsequent processing stage uses the selection signal for the corresponding IMF iteration stage delayed by the appropriate clock cycles to handle and store until the next envelope interpolation stage. BRAM data are read out on the falling edge of the clock 0.5 clock cycles before each stage’s selection signal to ensure BRAM read/write does not affect the maximum clock frequency. When the local mean of IMF7 is generated, it is sent to the IMF calculation module to calculate the difference with the previous stage’s mean, outputting IMF7 and generating a data-ready signal. The IMF7 extraction with module reuse can still operate at a 200 MHz clock frequency, with overall fault detection delay increased to 0.008 ms, which is still within acceptable limits. Meanwhile, 41% of LUTs, 39% of Registers, 82% of CARRY8, 71% of BRAM, and 86% of DSPs are saved.

4. Result

4.1. Reliability of Approximate Calculations

In the FPGA implementation, numerous approximate calculations based on CORDIC and lookup table (LUT) multipliers were employed to reduce computational latency, save computation time, and lower hardware costs. To decrease the computational load of post-FFT data processing, the FFT results were resampled to lower the precision for calculations. To minimize the resource consumption of the LUTs, the lookup tables provided only eight decimal places of precision. Additionally, due to the input interface width limitations of DSP slices, some data truncation was performed during energy accumulation and square root calculations. Furthermore, all operations were executed in fixed-point arithmetic due to FPGA constraints. These factors could potentially impact the validity of the final results. Therefore, the methods used in this process were simulated to ensure that the detection accuracy achieved on the FPGA aligns with the experimental results implemented on the ESP32. As shown in Figure 8, the simulation results indicate that even with a significant number of low-precision approximate calculations, a clear distinction between fault modes and normal modes can still be observed.

We attempted to improve the method using sampling localization for failed detections but were unable to succeed. As shown in Figure 8, the significance of fault features exhibits a certain periodicity. Combined with the need for sufficient sample lengths in EMD to extract required features, the dead time may be relatively long, leading to a failure in timely fault detection. Efforts are currently underway to replace relative Shannon entropy with SVM for outputting results.

4.2. Accuracy of Abnormal Recognition

Since the design and optimization of MCU and FPGA co-working had not yet been completed, the effectiveness of the actual operation was tested on the ESP32 MCU.

Table 1. Abnormal recognition accuracy.

Type of Mode	Recognition Accuracy (%)
No Fault	100%
Single Intact Stone in Coffee Bean	100%
Many Crashed Stone in Coffee Bean	91%
Single Crashed Stone in Coffee Bean	0%

shows that, in tests conducted using the ESP32 platform and the Mazzer 186C conical coffee grinder with 17.6 g of coffee beans and either a single 0.4 g stone or 0.4 g of crushed stones under espresso grinding settings, the stones and coffee beans are thoroughly mixed before being placed. The microphone front end is approximately 50 mm from the center of the grinder blade, with the microphone diaphragm oriented at 90 degrees to the coffee grinder casing. The fault detection method reliably identified both a single intact stone and multiple crushed stones with accuracy rates of 100% and 91%, respectively. All faults were detected during actual operations; however, in 9 out of 100 tests in the crushed stone group, the stones had already contacted the grinder blades at the time of fault detection, failing to meet the design goals.

This may be because crushed stones sink faster and tend to concentrate towards the center during grinder rotation. In this mode, the features generated may be more complex, potentially overlapping and canceling each other under different conditions, thus falling below the confidence interval over longer time spans. This may require further judgment by combining features from other IMFs. Additionally, in 25 tests using normal coffee beans (18 g per grind), no false positives were triggered. Tests with single, small, crushed stones also yielded a success rate of 0%. We believe that using an electric coffee grinding platform instead of a manual one to set more precise confidence intervals could help achieve better detection of single crushed stones. Furthermore, in the current detection process design, the information contained in the time domain and residuals was not effectively utilized [48,49]. We suggest that effectively leveraging this information to establish multiple evaluation criteria might aid in the detection of single crushed stones [50].

4.3. Resurce Consumption of FPGA

In the current FPGA implementation, the resource consumption is as shown in

Table 2. Abnormal recognition accuracy.

Logic Resource	Full Process	EMD Only w/o Reuse	EMD Only with Reuse
LUTs	4700	2094	1239
Registers	7267	3751	2283
CARRY8	219	122	22
F7 Muxes	59	0	1
Block RAM Tiles	18	14	4
DSPs	33	14	2

in the case of the full detection process, EMD only without any reuse of logic resource, and EMD with Time Division Multiplexing.

The comprehensive results from Vivado simulations indicate a power consumption of 1.44 W for all three cases above. The primary resource expenditure is concentrated in subsequent FFT processing, modulus calculation, energy normalization, and relative entropy computation. Therefore, we believe that relying on FPGA or CPLD in collaboration with a MCU to complete this detection process is feasible. After module reuse, the resource consumption for implementing the EMD algorithm and communication is sufficient to be executed on a small FPGA with 3 k LEs. With further optimization of some processes, it might even be possible to implement it on a 2 k LE FPGA. Offloading the subsequent computations to the MCU’s DSP can reduce resource consumption [20]. Modern MCUs have computational speeds for 64-point FFTs and modulus operations that approach those of FPGAs, and their performance in energy normalization and relative entropy calculations is adequate to meet the real-time processing requirements at the proposed sampling rates. Therefore, we suggest that having the MCU and FPGA collaboratively handle this process, with targeted optimizations to save the FPGA’s valuable hardware resources, is a more reasonable approach.

Due to funding constraint in our lab, we lack a complete testing process for FPGA experimental verification. For the part that involves the standalone EMD algorithm + FFT + calculating relative Shannon entropy output, the output accuracy is no different from that of the ESP32. The hardware resource consumption cannot be directly compared between FPGA and ESP32. When using FPGA, the delay is 0.002 ms in the no-time-multiplexed pipeline scenario and 0.008 ms in the time-multiplexed pipeline scenario, while the delay for the ESP32 is 20. 60 ms.

In the detection process, two different detection methods are designed for stones at the bottom and other positions. For example, a 12 kHz high-frequency spike triggered when a stone is placed at the bottom of the coffee beans will be detected by a filter and directly trigger an alarm. For other cases, the EMD algorithm is used for detection. In the experiment, the stones and coffee beans are thoroughly mixed before being placed, and the specific location of the stones is not experimentally tested. Additionally, due to the limitations of the coffee grinder structure and laboratory equipment, the descending speed of coffee beans at different distances from the axial center of the grinder could not be measured experimentally. Therefore, the impact of the physical position of the stone on the results also could not be quantified through simulation. It is certain that because the EMD algorithm requires a sufficiently long time series to achieve stable decomposition of the corresponding modes, there is at least a 0.5 s dead time in the detection. If the stone does not appear at the bottom of the coffee beans and descends to the grinder blade during the dead time, the detection will fail. Under the designed fixture, the geometric distance between the microphone’s front-end protective cover and the center of the coffee grinder blade is approximately 50 mm. During the fixture design, we found that the method’s effectiveness does not seem to be sensitive to the geometric distance and directivity between the microphone and the grinder blade, unless the microphone casing directly contacts the coffee grinder casing. The stones and coffee beans are thoroughly mixed before being placed. The microphone front end is approximately 50 mm from the center of the grinder blade, with the microphone diaphragm oriented at 90 degrees to the coffee grinder casing.

5. Conclusions

In coffee production, the presence of stones mixed with supplied coffee beans can lead to a variety of problems. Although suppliers have continuously endeavored to improve the methods and processes for screening coffee beans, ensuring reliability remains challenging. This paper presents a method to detect stones in supplied finished coffee beans during the grinding phase before the stones cause significant impact. The method determines whether stones are mixed into the coffee beans by analyzing the differences in the frequency of sound energy generated by the collision of coffee beans and stones with the grinder before the coffee grinder starts operating. After the grinder begins functioning, a method based on the Empirical Mode Decomposition (EMD) algorithm is employed to extract information from the sounds produced during operation, highlighting significant differences between fault modes and normal modes to ascertain the presence of stones in the coffee beans. Additionally, this paper proposes an FPGA implementation of the post-startup detection method to ensure real-time fault detection. Although this detection process has very low requirements on the FPGA’s operating frequency, certain simplifications of the FPGA computational process were still introduced to ensure compatibility across different FPGA hardware platforms. In tests conducted on the ESP32 platform, this method achieved excellent detection accuracy for intact stones that resemble coffee beans in appearance. However, the detection accuracy for many small, crushed stones still requires improvement, and it was entirely unable to detect single, small, crushed stones. We speculate that these issues might be further optimized or resolved by more fully utilizing the time-domain information of the signals that characterize fault modes, and the residual information generated through iterative EMD algorithm processes. These challenges necessitate further research and refinement. Furthermore, we discovered that the detection process on the FPGA after the system starts operating is not particularly economical, as many computations could be easily handled by the MCU. Consequently, we propose a concept where the MCU and FPGA collaboratively and efficiently complete the detection process in an economical and real-time manner. To support this concept, a scheme for implementing reuse within the EMD algorithm is presented. This scheme demonstrates that the proposed concept can be realized in a relatively economical way. However, we acknowledge that resource usage still needs further optimization, and the methods and processes for MCU and FPGA collaboration require additional research.

It is also noted that empirical wavelet transform (EWT) [51] and support vector machines (SVM) [52] could be potential directions for improving algorithm real-time performance and accuracy. Using six max peaks and geometric mean segmentation, the EWT analysis of a fault signal mixed with a single stone revealed a consistent amplitude-modulated signal in MRA2 of the multi-resolution analysis (MRA). In contrast, this pattern was not observed in signals with fragmented stones or fault-free conditions. This explains the significantly better accuracy in detecting a single stone. A comparison of FPGA-based EMD realization lists is found in

Table 3. Abnormal recognition accuracy.

	[53]	[54]	[55]	This Work w/o Reuse	This Work with Reuse
Clock Rate (Mhz)	12.5	50	46.44	200	200
Throughput (Mbps)	140	58.5	620	200	100
Interpolation Method	STI	STI/CSI/HA	STI/CSI	STI	STI
Architecture	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline
Data Format	Integer	Integer	Fixed Point	Fixed Point	Fixed Point

.

Since the amplitude frequency variation in MRA2 is faster than the minimum detection time required by current methods to avoid false positives, EWT could potentially achieve similar detection while offering better real-time performance [53,54,55]. Additionally, although no conclusive results have been achieved yet, combining EMD and EWT for noise reduction and multi-resolution analysis or applying EWT for time-frequency analysis of IMF7’s FFT might further improve detection accuracy, making these promising directions for future research. Moreover, setting a threshold for normalized relative Shannon entropy to output results requires the threshold to be relatively high to avoid false positives, which undoubtedly reduces detection sensitivity. Replacing relative Shannon entropy analysis with EWT or using SVM to process FFT outputs and generate detection results are reasonable alternatives. SVM can balance detection sensitivity and false positives better in two-class problems. Like EWT, SVM has the potential to capture time-frequency features, providing more information for fault classification [56]. Furthermore, SVM’s functions can all be implemented through MAC operations, making it well-suited for FPGA-based hardware acceleration and pipeline operations to enhance data throughput. We only extracted features characterizing fault modes from IMFs 6 and 7. Attempts to fuse the features extracted from these two IMFs for result output showed no significant improvement. In experiments, IMF7 demonstrated better performance in fault detection compared to IMF6, leading to the use of IMF7 alone for fault detection. We believe that further optimizing the logic resource consumption for IMFs extraction and communication to within 2 kLEs can further reduce costs. Efforts are being made in this direction, potentially involving changes to FPGA memory scheduling and management. However, these changes will undoubtedly impact latency, the maximum clock frequency of the FPGA, and the maximum input sampling signal frequency, requiring further improvements and validation.