Journal of Low Power Electronics and Applications

33 pages, 1072 KB

Open AccessReview

3D Integrated DNN Accelerators: Recent Trends and Future Prospects

by Abrar Abdurrob, Aristotelis Tsekouras, Evangelos Tzouvaras, Vasilis F. Pavlidis and Emre Salman

J. Low Power Electron. Appl. 2026, 16(2), 21; https://doi.org/10.3390/jlpea16020021 - 18 Jun 2026

Viewed by 535

The rapid growth of Deep Neural Networks (DNNs) has led to the development of application-specific DNN accelerators. Conventional 2D von Neumann architectures suffer from memory bandwidth limitations between the memory and the processing core. 3D DNN accelerators have emerged as a promising solution [...] Read more.

The rapid growth of Deep Neural Networks (DNNs) has led to the development of application-specific DNN accelerators. Conventional 2D von Neumann architectures suffer from memory bandwidth limitations between the memory and the processing core. 3D DNN accelerators have emerged as a promising solution by leveraging 3D integration to enable near-memory logic or in-memory computation. By shifting computation closer to memory, these accelerators significantly reduce data movement and therefore latency, resulting in more energy-efficient operations. Monolithic 3D (M3D) integration, in particular, enables high-bandwidth systems by utilizing high-density monolithic inter-tier vias (MIVs). This paper provides a critical review of recent advances in 3D DNN accelerators that combine near-memory and compute-in-memory with various 3D technologies, offering a useful discussion and future prospects of the available technologies and architectures that have advanced the performance of DNN accelerators. Particular attention is devoted to accelerators for emerging transformer-based large language model (LLM) networks due to the higher memory demands. Thermal-aware design techniques of 3D DNN accelerators are also discussed as a means to address the fundamental challenge of heat dissipation. A detailed review is finally conducted on package-level constraints, considering signal integrity, power delivery, and thermo-mechanical reliability. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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29 pages, 5987 KB

Open AccessReview

Wearable, Self-Powered Electronic Devices: Logical Framework for Transforming the Future of Digital Health

by Jegan Rajendran, Nimi Wilson Sukumari and Manikandan Rajendran

J. Low Power Electron. Appl. 2026, 16(2), 20; https://doi.org/10.3390/jlpea16020020 - 16 Jun 2026

Viewed by 663

Abstract

The increasing demand of digital technologies and their integration with wearable health devices provides an efficient trigger for next-generation wearable healthcare devices for long-term physiological monitoring. The advancement of energy harvesting mechanism, nanomaterial-based sensor fabrication and their integration with digital technologies have emerged [...] Read more.

The increasing demand of digital technologies and their integration with wearable health devices provides an efficient trigger for next-generation wearable healthcare devices for long-term physiological monitoring. The advancement of energy harvesting mechanism, nanomaterial-based sensor fabrication and their integration with digital technologies have emerged as a promising solution for transforming future of digital health. This study provides a comprehensive summary and framework for wearable self-powered electronic devices, enabling continuous, battery-free health monitoring and advancing the development of sustainable, next-generation digital healthcare systems. This review paper presents a broad and detailed overview of current technologies and sensors advancement in developing low-power wearable, self-powered electronic devices suitable for healthcare applications. The importance and reliable use of key energy harvesting approaches including triboelectric, piezoelectric, thermoelectric, and photovoltaic approaches are systematically presented which focused on development of energy efficient wearable devices. This review further examines the low-power circuit design strategies for flexible electronics focusing personalized healthcare monitoring. Current challenges and limitations related to advanced manufacturing of wearable health devices focusing on large-scale deployment are also analyzed. Finally, the key future research directions are outlined for advancing a next-generation intelligent digital health system. Full article

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15 pages, 3737 KB

Open AccessFeature PaperArticle

Design of an X-Band CMOS VCO with a Transformer-Coupled and Transconductance-Boosted Stacked Topology

by Yen-Ying Peng, Syu-Bin Li, Sen Wang and Chatrpol Pakasiri

J. Low Power Electron. Appl. 2026, 16(2), 19; https://doi.org/10.3390/jlpea16020019 - 15 Jun 2026

Viewed by 348

Abstract

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped [...] Read more.

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain K_VCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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23 pages, 1147 KB

Open AccessArticle

Thermal Nonuniformity-Aware Reliability Screening for Systolic AI Accelerators

by Larisa Goffman-Vinopal

J. Low Power Electron. Appl. 2026, 16(2), 18; https://doi.org/10.3390/jlpea16020018 - 31 May 2026

Viewed by 385

Abstract

AI accelerators increasingly operate under tight power, thermal, voltage, and timing margins, making workload-dependent thermal nonuniformity an important reliability concern. In systolic AI accelerators, localized activity concentration can create spatially uneven thermal stress, but thermal or timing-exposure analysis alone does not determine whether [...] Read more.

AI accelerators increasingly operate under tight power, thermal, voltage, and timing margins, making workload-dependent thermal nonuniformity an important reliability concern. In systolic AI accelerators, localized activity concentration can create spatially uneven thermal stress, but thermal or timing-exposure analysis alone does not determine whether such stress remains benign, becomes numerically masked, or propagates into silent corruption. This paper presents a cross-layer early-stage screening methodology for thermal nonuniformity-aware reliability analysis in systolic arrays. The framework links workload-aware activity extraction, relative power concentration modeling, diffusion-based thermal proxy analysis, an explicit thermal-to-timing stress abstraction, path class-aware corruption modeling, and clean/masked/silent outcome classification. The revised framework is formalized mathematically and evaluated across dense, low-dynamic-range, and sparse GEMM workloads under weight-stationary and output-stationary execution. To strengthen statistical and methodological confidence, the study includes 100-seed corruption reruns with Wilson confidence intervals, thermal scaling across

8 \times 8

,

16 \times 16

, and

32 \times 32

arrays, calibration sensitivity, path weight sensitivity, component ablations, and preliminary compact thermal reference alignment. The results show that sparse workloads consistently produce the largest thermal spread across tested array sizes, while dense and low-dynamic-range workloads remain more spatially uniform. Under the default calibrated screening regime at

16 \times 16

, sparse output-stationary and sparse weight-stationary cases reach 49% and 40% silent corruption rates, respectively, while dense cases remain mostly clean or masked and low-dynamic-range cases remain largely clean. Sensitivity and ablation experiments show that the sparse workload risk is not caused by one isolated modeling component, although the masked/silent split depends on path class weighting and thermal diffusion assumptions. The main contribution is not signoff-accurate silicon failure prediction, but a reproducible screening front end for identifying workload, dataflow, and path class combinations that deserve deeper thermal, timing, RTL-level, and application-level validation. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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14 pages, 4372 KB

Open AccessArticle

A Low-Power 68.4 dB Signal-to-Noise-and-Distortion Ratio Noise-Shaping SAR ADC for Biomedical Applications

by Thi Phuong Ha, The Khai Chu, Van Tung Nguyen, Orazio Aiello and Xuan Thanh Pham

J. Low Power Electron. Appl. 2026, 16(2), 17; https://doi.org/10.3390/jlpea16020017 - 7 May 2026

Viewed by 778

Abstract

This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both [...] Read more.

This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both infinite- and finite-impulse response filters to minimize quantization and kT/C noise. Additionally, it employs a low-power two-stage chopper amplifier to compensate for the offset voltage and enhance system stability. Validated according to the 180 nm CMOS process, the proposed ADC has an effective number of bits of 10.6, a signal-to-noise-and-distortion ratio of 68.4 dB, and a signal-to-noise ratio of 59.33 dB. With a compact area of 0.17 mm² and a power consumption of 650 µW from a 1.8 V supply, the proposal is well suited to biomedical sensor applications requiring strict accuracy and low energy consumption. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))

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17 pages, 2015 KB

Open AccessArticle

Efficient Battery State of Health Estimation Using Lightweight ML Models Based on Limited Voltage Measurements

by Mohammad Okour, Mohannad Alkhalil, Mutaz Al Fayad, Juhyun Bak, Kevin R. James, Sulaiman Mohaidat, Xiaoqi Liu, Fadi Alsaleem, Michael Hempel, Hamid Sharif-Kashani and Mahmoud Alahmad

J. Low Power Electron. Appl. 2026, 16(2), 16; https://doi.org/10.3390/jlpea16020016 - 21 Apr 2026

Viewed by 1175

Abstract

Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight [...] Read more.

Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight SoH-prediction framework validated on both physics-informed synthetic aging data and the NASA battery aging dataset. We evaluated Random Forest (RF) and Feedforward Neural Network (FNN) models that use only a limited number of samples from an early segment of the raw discharge voltage curve as input. Results show that RF consistently outperforms FNN across input sizes in deterministic or noise-free environments, achieving an RMSE of 0.07% SoH using just 5 voltage samples. In inherently stochastic experimental data, however, FNN can achieve an RMSE 50% lower than RF (1.28 vs. 2.87), but requires 37× more mathematical operations per inference. These findings emphasize the predictive value of the early-discharge-voltage region and demonstrate that compact, low-feature-complexity models can deliver accurate SoH estimates. Overall, the approach supports a goal of combining informed synthetic data with limited real measurements to build robust, scalable SoH predictors, reducing dependence on labor-intensive degradation testing and feature-heavy pipelines. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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19 pages, 5661 KB

Open AccessArticle

Low-Cost Smart Ammeter for Autonomous Contactless IoT Power Monitoring

by Nicolas Medrano, Diego Antolin, Daniel Eneriz and Belen Calvo

J. Low Power Electron. Appl. 2026, 16(2), 15; https://doi.org/10.3390/jlpea16020015 - 18 Apr 2026

Viewed by 1523

Abstract

The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The [...] Read more.

The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The differential configuration of the sensor module and the subsequent fully digital programmability in range and sensitivity, together with the included self-calibration and compensation circuits for mismatching, managed by a microcontroller, allow for optimum detection for both continuous and mains current with a resolution of 10 mA for input ranges of 2 A. The proposed ammeter power consumption and measurement accuracy in different scenarios are tested, including the power monitoring of an IoT-based device, obtaining results matched to those featured by a commercial oscilloscope current probe, which validates its suitability and reliability as autonomous low-cost probe for portable contactless power monitoring. Full article

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16 pages, 1361 KB

Open AccessArticle

RF/mm-Wave Frequency Doublers in CMOS Technology

by Manfredi Caruso, Andrea Ballo, Minoo Eghtesadi and Egidio Ragonese

J. Low Power Electron. Appl. 2026, 16(2), 14; https://doi.org/10.3390/jlpea16020014 - 13 Apr 2026

Viewed by 1248

Abstract

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, [...] Read more.

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, and spectral purity. The review covers several topologies from the standard push–push (PP) doubler to its power-efficient evolution, the complementary push–push (CPP) doubler. Furthermore, this paper focuses on more recent and advanced topologies, including the complementary common gate capacitive cross-coupled (CCGCCC) doubler. Finally, this work proposes and evaluates an improved version of the CCCGCC doubler, offering insights into the state of the art and future directions in mm-wave frequency multiplication. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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21 pages, 9981 KB

Open AccessArticle

Forward-Flyback Resonant Topology with Edge AI for MPPT Control in Solar Power Generation

by Juan Cruz-Cozar, Javier Mendez, Miguel Molina, Jorge Perez-Martinez, Alberto Martin-Martin, Noel Rodriguez and Diego P. Morales

J. Low Power Electron. Appl. 2026, 16(2), 13; https://doi.org/10.3390/jlpea16020013 - 12 Apr 2026

Viewed by 1359

Abstract

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the [...] Read more.

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the maximum possible energy from the solar source is crucial for the correct deployment of these distributed grids. In this work, system-level solutions are proposed for this application as follows: On the one hand, the use of novel resonant forward-flyback converters allows for a higher energy density than that of a conventional flyback and more relaxed withstand voltages on the switching elements. On the other hand, the implementation of maximum power point tracking algorithms for solar energy using Edge AI enables the deployment of algorithms that maximize the energy obtained locally. These improvements are shown by means of a prototype demonstrator, using cutting-edge microcontrollers and the implementation of a DC-DC power converter based on the proposed topology. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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18 pages, 3099 KB

Open AccessArticle

A 0.3 V Nanowatt Bulk-Driven CCII⁻ in 0.18-µm CMOS for Ultra-Low-Power Current-Mode Interfaces

by Giovanni Nicolini, Alessio Passaquieti, Giuseppe Scotti and Riccardo Della Sala

J. Low Power Electron. Appl. 2026, 16(2), 12; https://doi.org/10.3390/jlpea16020012 - 8 Apr 2026

Viewed by 607

Abstract

A 0.3 V nanowatt CCII⁻ is presented in 0.18

μ

m TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 [...] Read more.

A 0.3 V nanowatt CCII⁻ is presented in 0.18

μ

m TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are

β_{0} = 0.9452

(−0.48 dB) and

α_{0} = 0.9609

(≈−0.35 dB), with

- 3

dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding

R_{X} = 46.73

M

Ω

,

R_{Z} = 1.204

G

Ω

, and a very high input resistance

R_{Y} = 392

G

Ω

. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))

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32 pages, 8214 KB

Open AccessArticle

Static Voltage Stability Assessment of Renewable Energy Power Systems Based on DBN-LSTM Power Forecasting

by Qiang Wang, Libo Yang, Mengdi Wang, Bin Ma, Long Yuan, Shaobo Li and Zhangjie Liu

J. Low Power Electron. Appl. 2026, 16(2), 11; https://doi.org/10.3390/jlpea16020011 - 24 Mar 2026

Cited by 1 | Viewed by 1377

Abstract

High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A [...] Read more.

High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A low-conservativeness analytical criterion is first derived for static voltage stability margin assessment. Then, a hybrid Deep Belief Network–Long Short-Term Memory (DBN–LSTM) model is developed for accurate renewable power forecasting, capturing temporal variability and uncertainty. Finally, UFLS-based stability-constrained dispatch is formulated to prevent voltage collapse, enhance the system stability, and minimize RES curtailment. Simulations on a modified IEEE benchmark system demonstrate that the proposed approach improves voltage and frequency stability while maintaining high renewable energy utilization. Full article

(This article belongs to the Special Issue Energy Consumption Management in Electronic Systems)

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J. Low Power Electron. Appl., Volume 16, Issue 2 (June 2026) – 11 articles

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