Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Abstract

The effect of high- and low-temperature conditions on the performance of IGZO TFT and logic circuits were investigated in this work. In the temperature range of 250−350 K, the performance of the IGZO TFT did not show significant changes and exhibited a certain degree of high- and low-temperature resistance. When the temperature was below 250 K, as the temperature decreased, the threshold voltage (V_TH) of the IGZO TFT significantly increased, the field effect mobility (μ_FE) and the on state current (I_ON) significantly decreased. This is attributed to the lower excitation degree of charge carriers at extremely low temperatures, resulting in fewer charge carriers transitioning to the conduction or valence bands, and the formation of defects also limits carrier migration. When the temperature exceeded 350 K, as the temperature increased, more electrons could escape from the bandgap trap state and become free charge carriers, and the IGZO layer was thermally excited to produce more oxygen vacancies, resulting in higher μ_FE and lower V_TH. In addition, the drain current noise spectral density of IGZO TFT conformed to the 1/ƒ noise characteristic, and the degradation mechanism of IGZO TFT over a wide temperature range was confirmed based on the changes in noise spectral density at different temperatures. In addition, an inverter logic unit circuit was designed based on IGZO TFT, and the performance changes over a wide temperature range were analyzed. This lays the foundation for IGZO TFT to be applied in integrated circuits with harsh environments.

1. Introduction

In recent years, amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) has been widely used in various fields such as displays, sensors, memory, and neural morphology systems due to its unique advantages in off-state leakage current, carrier mobility, threshold voltage, and manufacturing process [1,2,3,4,5]. In addition, a-IGZO TFT has broad application prospects in the field of monolithic 3-D (M3D)-integrated circuits due to its high compatibility with complementary metal oxide semiconductors (CMOS), wide bandgap (E_g~3.05 eV), and excellent manufacturing yield characteristics [6,7,8,9]. Furthermore, considering that the electron conduction path in IGZO is mainly formed by the extended spherical 5s orbitals of In³⁺, the overlap between the 5s wave functions of adjacent In³⁺ is not sensitive to the disordered local structure of a-IGZO,s making IGZO TFT a potential device for applications in harsh environments [10,11].

Given the current promising development potential of IGZO TFTs in many fields, and with the push towards employing circuits fabricated in the latest technology for space and military environments, it is necessary to evaluate the performance changes of IGZO TFTs in extreme environments [12]. Current research indicates that amorphous materials have a more flexible atomic bond structure compared to crystalline silicon, and their structural plasticity leads to easy defect reconstruction, with the potential to achieve large-scale scalable radiation resistance [13]. The research on the radiation effects of IGZO TFT for space applications is also actively advancing, and preliminary results have been achieved [14,15,16,17,18,19,20]. In addition, the stable operating temperature range of commercial integrated circuits (ICs) is usually between 25–85 °C (298–358 K). However, with the development of aerospace, gas, down-hole oil, and other fields, the performance of semiconductor devices and circuits in higher- or lower-temperature ranges is facing enormous challenges [21]. In order to comprehensively explore the potential of IGZO TFT for harsh environmental applications, it is necessary to study the performance changes of IGZO TFT and related circuits over a wide temperature range. At present, there has been research progress on IGZO TFT under high-temperature conditions, and the device exhibits strong temperature dependence under high-temperature conditions [22,23]. However, the degradation mechanism of IGZO TFT and related logic unit circuits over a wide temperature range is currently unclear.

In this work, IGZO TFT devices with good electrical performance were prepared using radio frequency (RF) magnetron sputtering technology. The inverter unit circuit was designed based on IGZO TFT. The influence of temperature on the electrical performance of IGZO TFT and an inverter circuit was studied within a wide temperature range of 8–475 K, and the degradation mechanism of the device was analyzed based on the relationship between key electrical parameters and temperature. This study aims to provide reference for promoting the application of IGZO TFT and related circuits in harsh environments.

2. Devices and Methods

The IGZO TFTs were fabricated using a backed-gate process on the 8-inch pilot CMOS line at the Institute of Microelectronics of the Chinese Academy of Sciences. For the device fabrication, a 200 nm SiO₂ buffer layer was deposited on a silicon substrate through plasma-enhanced chemical vapor deposition (PECVD). Subsequently, 60 nm thick Mo layer was sputtered and subjected to dry etching to form a bottom gate electrode. HfO₂ with a thickness of 15 nm was deposited as a gate insulator layer (GI) using the PECVD method. Then, a 25 nm thick a-IGZO film was deposited and patterned using radio frequency magnetron sputtering technology in an Ar/O₂ atmosphere at room temperature. The atomic ratio of the IGZO film was In:Ga:Zn = 1:1:1, the sputtering power was 200 W, and the pressure was 1 mTorr. Mo with a thickness of 60 nm was sputtered and patterned to form the source and drain electrodes, and a 100 nm thick SiO₂ passivation layer was deposited using the PECVD method. Finally, a-IGZO TFT devices were prepared by high-temperature annealing treatment for 1 hour in a N₂ atmosphere at 350 °C to improve their electrical properties. The key process steps for IGZO TFT device manufacturing are shown in Figure 1a.

The transmission electron microscope (TEM) image was obtained by using a focused ion beam (FIB) to cut the cross-section of the device along the channel length direction, as shown in Figure 1b, where each layer of device structure can be clearly observed. Figure 1c shows high-resolution transmission electron microscopy (HRTEM) image, and the relatively clear and sharp interface on the IGZO/HfO₂ film indicates good film quality. Figure 1d shows the fast Fourier transform (FFT), which exhibits typical diffuse ring characteristics, indicating that IGZO is amorphous. The elemental composition of IGZO TFT was analyzed using an energy dispersive spectrometer (EDS), as shown in Figure 1e. After O₂ annealing, the elemental densities of Si, Ga, and Hf remained basically unchanged, but the O concentration in the a-IGZO channel increased, indicating oxygen permeation and possible filling of oxygen vacancies during the O₂ treatment process, which helps to improve the quality of the IGZO thin film.

The gate width (W) and length (L) of the IGZO TFT used are 2 μm and 0.5 μm, respectively. The low-temperature test was conducted in the Institute of Physical Chemistry Technology, Chinese Academy of Sciences, and the low-temperature test was controlled and adjusted within the range of 8–300 K through Lake Shore CRX. The high-temperature test was performed on the Cascade SUMMIT 12,000 B semi-automatic probe platform of the Institute of Microelectronics, Chinese Academy of Sciences. The probe platform incorporates a thermal chuck, and its temperature can be controlled through the ESPEC ETC-200 L unit. Measurements were carried out in the range of 300–475 K. In high-temperature testing, the I_D–V_G and I_D–V_D curves of the IGZO TFT were first tested at room temperature (300 K), and then, the temperature was increased in steps of 25 K until 475 K. At each temperature point, the I_D–V_G and I_D–V_D curves of the device were tested. In low-temperature testing, the device performance at room temperature was also initially tested as a reference, and then, the temperature was decreased in steps of 50 K until 10 K. At each temperature point, the I_D–V_G and I_D–V_D curves of the device were tested.

3. Experimental Results and Discussion

The transfer characteristics (I_D–V_G) of a-IGZO TFTs were measured at various temperatures T (from 8 to 475 K) for the gate voltages V_G ranging from −3 to 4 V with a fixed drain voltage V_D = 1 V, as shown in Figure 2. In the low-temperature range of 8–300 K, the I_D–V_G curve shows a positive shift with the temperature decreases, while in the high-temperature range of 300–475 K, the I_D–V_G curve shows a negative shift with the temperature increases. When the temperature reaches 475 K, the drain current seriously deviates from the normal value within the measurable voltage range, and the device cannot turn off normally. The gate control ability of the IGZO TFT is severely weakened under high temperature.

The key electrical parameters that affect the static characteristics of IGZO TFT include threshold voltage (V_TH), field effect mobility (μ_FE), subthreshold swing (SS), and current switching ratio (I_ON/I_OFF). The extraction of V_TH adopts the constant-current method in this work. The V_TH is defined as the particular gate voltage (V_G) at which drain current (I_D) = 10⁻⁸ × (W/L) A [24]. The μ_FE and SS of IGZO TFT is calculated according to the Equations (1) and (2), respectively, where C_OX is the gate dielectric capacitance per unit area [25]. C_OX is calculated by the Equation (3).

$${\mu }_{\mathrm{FE}}=\frac{\mathrm{L}}{W{C}_{OX}{V}_{DS}}\cdot \frac{d{I}_D}{d{V}_G}$$

(1)

$$SS=(\frac{d\log (I_D)}{d{V}_G}{)}^{-1}{|}_{\max }$$

(2)

$$C_{OX}=\frac{{\epsilon }_0\cdot {\epsilon }_{OX}}{t_{OX}}$$

(3)

where ε₀ is the vacuum dielectric constant, and the value is 8.85 × 10⁻¹⁴ F/cm; ε_OX is the oxide layer dielectric constant, and the value is 20; t_OX is the thickness of the oxide layer, and the value is 15 nm. These parameters are inputted into the Equation (4), it can be calculated C_OX = 1.18 × 10⁻⁶ F/cm².

Key parameters that characterize the electrical performance of IGZO TFT are extracted according to the I_D–V_G curves at various temperatures in Figure 2, including ΔV_TH, ΔSS, Δμ_FE, and ΔI_ON. The variation of each parameter with temperature is shown in Figure 3. These parameters are all based on 300 K as a reference point. Taking ΔV_TH as an example, ΔV_TH represents the difference between the threshold voltage at a specific temperature and the threshold at room temperature, as shown in Equation (4).

$$\Delta V_{TH}=V_{TH@T}-V_{TH@300K}$$

(4)

Figure 3 shows that there is no significant change in the key electrical parameters of the IGZO TFT within the temperature range of 250–350 K, indicating that the device exhibits a certain degree of high- and low-temperature resistance.

When the temperature is below 250 K, as the temperature decreases, the V_TH of the IGZO TFT significantly increases, and the μ_FE and I_ON significantly decrease. This is attributed to the lower excitation degree of charge carriers at extremely low temperatures, resulting in fewer charge carriers transitioning to the conduction or valence bands, and the formation of defects also limits carrier migration [8,21]. When the temperature exceeds 350 K, as the temperature increases, more electrons can escape from the sub bandgap trap state and become free charge carriers, and the IGZO layer is thermally excited to produce more oxygen vacancies, resulting in larger I_ON and smaller V_TH [22,26]. Therefore, the observed lower V_TH with increasing temperature may be due to the combined effect of these free electrons escaping from the sub bandgap trap state together with the generation of oxygen vacancies because of thermal excitation [23,27]. The increase in Δμ_FE is also attributed to the increase in thermal energy provided by high temperatures, which increases the kinetic energy of charge carriers and reduces the scattering mechanism that hinders their movement. Furthermore, within the temperature range of 8 K to 450 K, the ΔSS shows a slight increasing trend. When the temperature reaches 475 K, the ΔSS abnormally increases. This may be related to the fact that the oxygen vacancies generated by thermal excitation provide more traps, and charge capture occurs in the gate oxide through thermally assisted tunnelling, leading to an increase in ΔSS [28].

The relationship between the I_D–V_D curves and temperature of a-IGZO TFT is shown in Figure 4. In the low-temperature range, the I_D decreases with decreasing temperature; in the high-temperature range, the I_D increases with increasing temperature.

The variation relationship between a-IGZO TFT devices and temperature was simulated using TCAD. Specifically, the a-IGZO mobility model related to lattice temperature was used to simulate the changes in device electrical characteristics with temperature. The mobility model was designed to work in conjunction with the defect density model of electronic states [29]. Physical models such as the IGZO.TOKYO temperature model, Shockley–Read–Hall (SRH) generation and recombination, and Fermi statistical model were used in the simulation process [30]. The I_D–V_D curve obtained from TCAD simulation showed a consistent trend with the experimental test results as a function of temperature. Figure 5 shows the variation curve of channel electron concentration with temperature in TCAD simulation. As the temperature increases, the channel electron concentration significantly increases.

Figure 6a,c show the linear temperature dependence of the logarithm of I_D and 1/kT under different V_G voltages at low and high temperatures, respectively, and satisfies the Arrhenius relationship. The relationship between drain current and temperature is described by the Arrhenius Equation (5) [31,32].

$$I_{DS}=I_{DS0}\exp (-\frac{E_A}{kT})$$

(5)

where k is the Boltzmann constant, T is the temperature, E_A is the active energy, I_DS0 is the pre-factor, and E_A and I_DS0 are gate-voltage-dependent quantities.

The transport of charge carriers in channels is mainly influenced under different temperatures and V_G by three transport mechanisms, namely variable range hopping (VRH), trap-limited conduction (TLC), and percolation [33]. Among them, when V_G is small, at lower temperatures, carriers in the tail states lack sufficient thermal energy to cross the mobility edge (above a specific energy level near the conduction band minimum), and hence, transport is dominated by carriers undergoing VRH, tunneling between localized tail states, with lower carrier mobility in the channel, resulting in small I_D. At higher temperatures, Fermi-level (E_F) in the localized tail states and transport is dominated by TLC where carriers are thermally excited from the localized tail states to the extended states above mobility edge, resulting in an increase in carrier mobility and I_D compared to low temperatures; when V_G is large, as E_F efficiently moves above the mobility edge, percolation-dominated transport is observed for all temperatures, with higher carrier mobility in the channel, resulting in large I_D.

The activation energy of drain current shows differences in the temperature ranges of 50–150 K, 200–300 K, 300–375 K, and 400–475 K. The activation energy corresponding to different V_G in the higher-temperature region is generally higher than that in the lower-temperature region. Specifically, Figure 6b,d summarize the variation curves of activation energy with gate voltage over different temperature ranges. This is because for amorphous semiconductor TFTs, most of the charge induced by the gate electric field goes into the tail states, with a small fraction going into the conduction band [34]. As the gate voltage increases, the movement of E_F towards E_C leads to a change of the occupancy of the localized state, which in turn leads to a gradual decrease in activation energy [22].

Figure 7 shows the I_D–V_G curves with V_D = 0.1 V and V_D = 1 V under different temperatures. Usually, the V_TH shift in short-channel TFT devices is denoted by drain-induced barrier lowering (DIBL), which originates from the effective lowering of the barrier for current conducting between source and channel [35,36]. To determine the DIBL characteristics, we used the DIBL factor (λ_DIBL) defined in the Equation (6) [36].

$${\lambda }_{DIBL}=\frac{V_T(@V_{D1}=0.1\mathrm{V})-V_T(@V_{D2}=1\mathrm{V})}{V_{D2}-V_{D1}}$$

(6)

It is worth noting that when IGZO TFT is exposed to harsh temperature environments, such as temperatures below 150 K and above 425 K, the DIBL effect becomes more severe, as shown in Figure 7b,d. The reason is as follows: At extremely low temperature, the carrier mobility and density decrease, resulting in a more uneven electric field between the gate and channel of the transistor, making it more difficult to control the channel and leading to adverse DIBL effects; at high temperature, the thermally excited oxygen atoms will leave their original positions and generate vacancies as the temperature increases. Oxygen vacancies act as electron donors as V_O = V_O²⁺ + 2e⁻ [37,38]. The oxygen vacancies near the drain side and source side affect the overall carrier concentration of the active channel. As V_D increases, V_TH shifts in the negative direction, and the number of thermally excited oxygen atoms increases with temperature, resulting in a more severe DIBL. The Δλ_DIBL of IGZO TFT at different temperatures is summarized in

Table 1. The Δλ_DIBL of IGZO TFT varies with temperature.

T (K)	ΔλDIBL (mV/V)	T (K)	ΔλDIBL (mV/V)
8	355.5	325	10.52
50	75.5	350	−11.08
100	62.5	375	−10.98
150	29.2	400	33.32
200	15.5	425	133.32
250	10.5	450	466.22
300	0	475	>1166.2

.

In order to analyze the effect of temperature on the charge transfer mechanism of IGZO TFT, the noise characteristics of the device at different temperatures were studied. At room temperature, the normalized drain current noise spectral density (S_ID/I_D²) and the transconductance to drain current squared (g_m/I_D)² of IGZO TFT exhibited an approximate trend of variation with drain current, as shown in Figure 8a. Among them, the S_ID/I_D² was extracted at ƒ = 0.1 Hz for the device. This indicates that the noise spectral density and transconductance of IGZO TFT satisfy the carrier number fluctuation (CNF) theory shown in Equations (7) and (8) [3,39].

$$\frac{S_{ID}}{{I_D}^2}=(\frac{g_m}{I_D}{)}^2\cdot S_{Vfb}$$

(7)

with

$$S_{Vfb}=\frac{q^2{N}_{t}kT\lambda }{WL{C_{ox}}^{2}f}$$

(8)

where S_Vfb is the power spectral density of flat-band voltage fluctuations, N_t is the volume trap density, kT is the thermal energy, λ is the oxide tunneling attenuation distance, WL is the channel area, C_ox the gate oxide capacitance per unit area, and f is the frequency [40]. The extracted value of S_Vfb is 8.9 × 10⁻¹³ V²/Hz for the IGZO TFT device in this work.

The relationship between the drain current noise spectral density and frequency at different temperatures is shown in Figure 8b. The S_ID of the drain current increases with the increase of temperature, which confirms the degradation mechanism of the active layer of IGZO TFT devices being thermally excited under high-temperature conditions, resulting in an increase in carrier concentration.

The inverter circuit was designed based on the IGZO TFT device, as shown in Figure 9. The transistor T1 with gate drain short circuit is used as the load transistor, T2 is the driving transistor, and the aspect ratios of T1 and T2 are 2/0.5 (μm) and 30/0.5 (μm), respectively. The purpose of using a large-sized T2 is to provide sufficient driving capacity for the inverter to increase output swing. The voltage transmission characteristic (VTC) curve of the inverter was tested at different temperatures and is shown in Figure 8, where the power supply voltage V_DD = 3 V. In low-temperature environments, the VTC curve shifts to the right as the temperature decreases; in a high-temperature environment, the VTC curve moves horizontally to the left with the temperature increases. This is consistent with the trends of the I_D–V_G curves of IGZO TFT in Figure 2a,b under low- and high-temperature environments, respectively. This is reasonable because compared to the output drain current of a single transistor, the presence of load transistor T1 in the inverter converts the drain current of transistor T2 into output voltage.

In order to analyze the impact of temperature on the inverter circuit, key parameters affecting inverter performance, such as noise margin values and switching thresholds, were extracted based on the VTC curves at different temperatures. At 300 K, the input low (V_IL) and high (V_IH) voltage and the output low (V_OL) and high (V_OH) voltage were extracted from the voltage unit gain points (dV_OUT/dV_IN = −1), respectively. The specific relationship between the key parameters of the inverter and temperature is shown in Figure 10. Both the high noise margin (N_MH = |V_OH-V_IH|) and low noise margin (N_ML = |V_IL-V_OL|) show an increasing trend with the increased temperature [41]. The switching threshold voltage (V_M) of the inverter is defined as the point where V_IN = V_OUT [42]. It is expected that the V_M is located near the midpoint of the voltage swing (V_DD/2). As shown in Figure 8, it can be seen that the V_M shows a decreasing trend with the temperature increasing.

4. Conclusions

In this work, the electrical performance of IGZO TFT devices and related circuits were studied in the wide temperature range of 8–475 K. The experimental results show that within the range of 250–350 K, the IGZO TFT device is less affected by temperature and exhibits high- and low-temperature resistance. When the temperature exceeds this range, the device exhibits a certain degree of performance degradation with the temperature increases or decreases, and the DIBL effect of the device will gradually become significant. When the temperature reaches a high temperature of 475 K, the device cannot turn off normally, indicating that the gate control ability of the device is seriously affected at high temperatures. The 1/ƒ noise characteristics of the device show a significant increase in noise spectral density with increasing temperature, indicating that the IGZO active layer is thermally excited under high-temperature conditions, leading to an increase in carrier concentration. This work provides a reference for the application research of IGZO-based integrated circuits in harsh environments.