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20 pages, 8877 KiB

Open AccessArticle

Control of a Modified Switched-Capacitor Boost Converter

by Benjamin Ošlaj and Mitja Truntič

Electronics 2022, 11(4), 654; https://doi.org/10.3390/electronics11040654 - 19 Feb 2022

Cited by 3 | Viewed by 2646

Abstract

Switched-capacitor converters and their alternatives have been shown to provide high efficiency with high power densities on smaller volumes, and can thereby be a suitable choice for energy harvesting. This paper proposes a hybrid power architecture based on a switched-capacitor topology and a [...] Read more.

Switched-capacitor converters and their alternatives have been shown to provide high efficiency with high power densities on smaller volumes, and can thereby be a suitable choice for energy harvesting. This paper proposes a hybrid power architecture based on a switched-capacitor topology and a boost converter that can be used for such purposes. A switching capacitor circuit can achieve any voltage ratio, allowing a boost converter to increase the input voltage to higher voltage levels. The first stage is unregulated with high-efficiency voltage conversion. The boost stage provides a regulated voltage output on such a converter. Rather than cascading two converters, their operation is integrated for the output voltage regulation. One major problem of switched-capacitor converters is output voltage regulation, which is solved by the interconnection of the power stages. The simplicity and robustness of the solution provide the possibility to achieve higher voltage ratios than cascading boost converters and provide higher efficiency. The converter’s size and cost can be improved with the integration of switching capacitors in DC-DC converter structures. A converter prototype has been designed, modelled, and built for the input voltage level of 2 V and power level of 5 W. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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29 pages, 4216 KiB

Open AccessArticle

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

by Juan David Espitia Castillo, Enrique Cantó Navarro and Enric Vidal-Idiarte

Electronics 2022, 11(3), 447; https://doi.org/10.3390/electronics11030447 - 2 Feb 2022

Cited by 2 | Viewed by 3420

Abstract

The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), [...] Read more.

The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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18 pages, 4157 KiB

Open AccessArticle

Model Predictive Control Scheme of a Four-Level Quasi-Nested Converter Fed AC-Drive, with dc-Link Voltage-Drift Compensation

by Carlos A. Reusser and Ramón Herrera

Electronics 2022, 11(3), 333; https://doi.org/10.3390/electronics11030333 - 21 Jan 2022

Viewed by 2273

Abstract

In this paper, a Model Predictive Control (MPC) strategy is introduced for its application in a four-level quasi-nested topology, feeding an Interior Permanent Magnet Synchronous Machine (IPMSM) AC-drive. The proposed control strategy is capable to synthesize the required output space vectors to ensure [...] Read more.

In this paper, a Model Predictive Control (MPC) strategy is introduced for its application in a four-level quasi-nested topology, feeding an Interior Permanent Magnet Synchronous Machine (IPMSM) AC-drive. The proposed control strategy is capable to synthesize the required output space vectors to ensure perfect tracking of the AC-drive speed reference under different loading conditions, while also ensuring voltage balance between the dc-link capacitors. The proposed converter topology is based on a reduced number of components compared to other mature converter topologies, such as the neutral-point clamped converter (NPC) or the active neutral-point clamped converter (ANPC) topologies, when compared in terms of the number of output voltage levels, since this quasi-nested topology does not require passive clamping devices such as diodes or active switches. Moreover, no floating dc-link capacitors with asymmetrical voltage levels are employed, thus simplifying the dc-link capacitor voltage balance mechanism. This work presents the switching operation principles and MPC control law when supplying an IPMSM AC-drive load are addressed in detail. Simulation and validation results using a Hardware in the Loop (HIL) prototype under different operation conditions are presented in order to validate the proposed converter topology and control strategy. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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23 pages, 5596 KiB

Open AccessEditor’s ChoiceArticle

Stability Analysis of Power Hardware-in-the-Loop Simulations for Grid Applications

by Simon Resch, Juliane Friedrich, Timo Wagner, Gert Mehlmann and Matthias Luther

Electronics 2022, 11(1), 7; https://doi.org/10.3390/electronics11010007 - 21 Dec 2021

Cited by 14 | Viewed by 4093

Abstract

Power Hardware-in-the-Loop (PHiL) simulation is an emerging testing methodology of real hardware equipment within an emulated virtual environment. The closed loop interfacing between the Hardware under Test (HuT) and the Real Time Simulation (RTS) enables a realistic simulation but can also result in [...] Read more.

Power Hardware-in-the-Loop (PHiL) simulation is an emerging testing methodology of real hardware equipment within an emulated virtual environment. The closed loop interfacing between the Hardware under Test (HuT) and the Real Time Simulation (RTS) enables a realistic simulation but can also result in an unstable system. In addition to fundamentals in PHiL simulation and interfacing, this paper therefore provides a consistent and comprehensive study of PHiL stability. An analytic analysis is compared with a simulative approach and is supplemented by practical validations of the stability limits in PHiL simulation. Special focus is given on the differences between a switching and a linear amplifier as power interface (PI). Stability limits and the respective factors of influence (e.g., Feedback Current Filtering) are elaborated with a minimal example circuit with voltage-type Ideal Transformer Model (ITM) PHiL interface algorithm (IA). Finally, the findings are transferred to a real low-voltage grid PHiL application with residential load and photovoltaic system. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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30 pages, 10254 KiB

Open AccessFeature PaperArticle

Wireless Power Transfer Using Double DD Coils

by Nataša Prosen, Jure Domajnko and Miro Milanovič

Electronics 2021, 10(20), 2528; https://doi.org/10.3390/electronics10202528 - 17 Oct 2021

Cited by 17 | Viewed by 4106

Abstract

This paper deals with a wireless power transfer system where a novel structure of transmitting/receiving double DD coils is applied. This system uses two identical double D (DD) transmitter coils stacked on each other to transfer power to two stacked receiver coils. The [...] Read more.

This paper deals with a wireless power transfer system where a novel structure of transmitting/receiving double DD coils is applied. This system uses two identical double D (DD) transmitter coils stacked on each other to transfer power to two stacked receiver coils. The power is transmitted simultaneously and independently through both transmitter coils to the receiving coils. The magnetic field of the first coil does not interfere with the second coil. Both transmitter and receiver coils are placed on each other and occupy the same footprint, so there is no need for increased space. This can lead to an interesting wireless power transfer system—from single load to double the load and higher power transfer density. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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36 pages, 32093 KiB

Open AccessArticle

Sensorless Control of PMSM Based on Backstepping-PSO-Type Controller and ESO-Type Observer Using Real-Time Hardware

by Claudiu-Ionel Nicola, Marcel Nicola and Dan Selișteanu

Electronics 2021, 10(17), 2080; https://doi.org/10.3390/electronics10172080 - 27 Aug 2021

Cited by 12 | Viewed by 3245

Abstract

In the case of using a Permanent Magnet Synchronous Motor (PMSM) linear model of limited-range parametric variations and of relatively low dynamic of the load torque, the Field Oriented Control (FOC) type strategy ensures good performance of the PMSM control. Therefore, when using [...] Read more.

In the case of using a Permanent Magnet Synchronous Motor (PMSM) linear model of limited-range parametric variations and of relatively low dynamic of the load torque, the Field Oriented Control (FOC) type strategy ensures good performance of the PMSM control. Therefore, when using a non-linear model of wide-range parametric variations and of high dynamic of the load torque, a backstepping-type controller is proposed, whose tuning parameters are optimized by using a Particle Swarm Optimization (PSO) method. By designing an Extended State Observer (ESO), which provides a good estimate of the PMSM rotor position and speed under uncertainty conditions and with a response time shorter than that of the backstepping-type controller, this observer can be incorporated into the PMSM sensorless control system. The superior performance of the proposed sensorless control system based on the backstepping-PSO-type controller and an ESO-type observer is demonstrated through numerical simulations. Given that the real-time implementation of the control algorithms and observers in an embedded system is a difficult task, consisting of several steps, it is presented after the numerical simulations, which can be assimilated into the Software-in-the-Loop (SIL) step, the Processor-in-the-Loop (PIL) intermediate step, and the Hardware-in-the-Loop (HIL) final step. A comparison between the backstepping-PSO-type controller and the PI-PSO-type controller is presented by means of the real-time implementation of these controllers and demonstrates the superiority of the backstepping-PSO-type controller. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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12 pages, 617 KiB

Open AccessFeature PaperArticle

Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

by Eva M. Cirugeda-Roldán, María Sofía Martínez-García, Alberto Sanchez and Angel de Castro

Electronics 2021, 10(16), 1952; https://doi.org/10.3390/electronics10161952 - 13 Aug 2021

Cited by 4 | Viewed by 2135

Abstract

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT [...] Read more.

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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27 pages, 15596 KiB

Open AccessArticle

Single-Shunt Three-Phase Current Measurement for a Three-Level Inverter Using a Modified Space-Vector Modulation

by Haris Kovačević, Lucijan Korošec and Miro Milanovič

Electronics 2021, 10(14), 1734; https://doi.org/10.3390/electronics10141734 - 19 Jul 2021

Cited by 8 | Viewed by 3109

Abstract

This article presents a single-shunt measurement of a three-level inverter using a modified space-vector modulation to reconstruct the three-phase load current. The proposed method was implemented on a digital signal processor (DSP), and the algorithm was verified in the laboratory experiment. Through the [...] Read more.

This article presents a single-shunt measurement of a three-level inverter using a modified space-vector modulation to reconstruct the three-phase load current. The proposed method was implemented on a digital signal processor (DSP), and the algorithm was verified in the laboratory experiment. Through the work, it was proven that the single-shunt three-phase current measurement could be performed using the space-vector modulation for three-level inverters in an analogous way to ordinary three-phase inverters. Three-phase current reconstruction for ordinary three-phase inverters was performed using the ordinary space-vector modulation with eight vectors, but for three-level inverters, 21 vectors were available. When the inverter was working on the edges between two vectors, the modulation disturbances appeared as current spikes. This problem was solved using the modified SVM performed by shifting the SVM signals. Carefully designed signal shifting (vector injection) demonstrated an excellent reconstruction of the three-phase load currents that were single-shunt measured. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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19 pages, 6115 KiB

Open AccessArticle

HIL Simulation of a Tram Regenerative Braking System

by Tomislav Pavlović, Ivan Župan, Viktor Šunde and Željko Ban

Electronics 2021, 10(12), 1379; https://doi.org/10.3390/electronics10121379 - 9 Jun 2021

Cited by 7 | Viewed by 3512

Abstract

Regenerative braking systems are an efficient way to increase the energy efficiency of electric rail vehicles. During the development phase, testing of a regenerative braking system in an electric vehicle is costly and potentially dangerous. For this reason, Hardware-In-the-Loop (HIL) simulation is a [...] Read more.

Regenerative braking systems are an efficient way to increase the energy efficiency of electric rail vehicles. During the development phase, testing of a regenerative braking system in an electric vehicle is costly and potentially dangerous. For this reason, Hardware-In-the-Loop (HIL) simulation is a useful technique to conduct the system’s testing in real time where the physical parts of the system are replaced by simulation models. This paper presents a HIL simulation of a tram regenerative braking system performed on a scaled model. First, offline simulations are performed using a measured speed profile in order to validate the tram, supercapacitor, and power grid model, as well as the energy control algorithm. The results are then verified in the real-time HIL simulation in which the tram and power grid are emulated using a three-phase converter and LiFePO₄ batteries. The energy flow control algorithm controls a three-phase converter which enables the control of energy flow within the regenerative braking system. The results validate the simulated regenerative braking system, making it applicable for implementation in a tram vehicle. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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20 pages, 1097 KiB

Open AccessArticle

Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters

by Elyas Zamiri, Alberto Sanchez, Marina Yushkova, Maria Sofia Martínez-García and Angel de Castro

Electronics 2021, 10(8), 926; https://doi.org/10.3390/electronics10080926 - 13 Apr 2021

Cited by 25 | Viewed by 4316

Abstract

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB [...] Read more.

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effort. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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15 pages, 4246 KiB

Open AccessArticle

Generalized Circuit Averaging Technique for Two-Switch PWM DC-DC Converters in CCM

by Sumukh Surya and Sheldon Williamson

Electronics 2021, 10(4), 392; https://doi.org/10.3390/electronics10040392 - 5 Feb 2021

Cited by 13 | Viewed by 3310

Abstract

Design of DC-DC converters like Cuk and SEPIC, which are fourth-order converters, play a vital role in the design of electric vehicle (EV) charging systems and drivers for LED. These converters possess a unique feature of input current being continuous due to the [...] Read more.

Design of DC-DC converters like Cuk and SEPIC, which are fourth-order converters, play a vital role in the design of electric vehicle (EV) charging systems and drivers for LED. These converters possess a unique feature of input current being continuous due to the presence of an inductor in series with the supply voltage. In the present work, a generalized approach for obtaining the frequency response of the transfer function of the duty cycle to output voltage (G_vd) for converters operating in continuous conduction mode (CCM) having two switches is proposed. A practical Cuk converter and SEPIC operating in CCM were selected and their analyses in open loop were studied using the LTSpice simulation tool. The behavior of the output voltage and inductor currents under variable ESR’s (equivalent series resistance) of inductors was studied. It was observed that G_vd of these converters was unstable. Hence, an appropriate controller to stabilize the system and achieve a proper gain margin and phase margin in closed-loop operation is required. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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17 pages, 17937 KiB

Open AccessArticle

An MPPT Strategy Based on a Surface-Based Polynomial Fitting for Solar Photovoltaic Systems Using Real-Time Hardware

by Catalina González-Castaño, Leandro L. Lorente-Leyva, Javier Muñoz, Carlos Restrepo and Diego H. Peluffo-Ordóñez

Electronics 2021, 10(2), 206; https://doi.org/10.3390/electronics10020206 - 17 Jan 2021

Cited by 17 | Viewed by 3754

Abstract

This paper presents an optimal design of a surface-based polynomial fitting for tracking the maximum power point (MPPT) of a photovoltaic (PV) system, here named surface-based polynomial fitting (MPPT-SPF). The procedure of the proposed MPPT-SPF strategy is based on a polynomial model to [...] Read more.

This paper presents an optimal design of a surface-based polynomial fitting for tracking the maximum power point (MPPT) of a photovoltaic (PV) system, here named surface-based polynomial fitting (MPPT-SPF). The procedure of the proposed MPPT-SPF strategy is based on a polynomial model to characterize data from the PV module with a global fit. The advantage of using polynomials is that they provide a good fit within a predefined data range even though they can diverge greatly from that range. The MPPT-SPF strategy is integrated with a DC-DC boost converter to verify its performance and its interaction with different control loops. Therefore, the MPPT strategy is applied to the reference outer PI control loop, which in turn provides the current reference to the inner current loop based on a discrete-time sliding current control. A real-time and high-speed simulator (PLECS RT Box 1) and a digital signal controller (DSC) are used to implement the hardware-in-the-loop system to obtain the results. The proposed strategy does not have a high computational cost and can be implemented in a commercial low-cost DSC (TI 28069M). The proposed MPPT strategy is compared with a conventional perturb and observe method to prove its effectiveness under demanding tests. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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Review

Jump to: Research

14 pages, 3698 KiB

Open AccessReview

Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters

by Daniel Tormo, Ricardo Vidal-Albalate, Lahoucine Idkhajine, Eric Monmasson and Ramon Blasco-Gimenez

Electronics 2022, 11(5), 719; https://doi.org/10.3390/electronics11050719 - 25 Feb 2022

Cited by 4 | Viewed by 1906

Abstract

This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the [...] Read more.

This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC controller switches from the measured voltages to their estimated counterparts. As for the digital implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq-7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz system clock, and the synchronization with the analog to digital acquisition chain was made with a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including the time/area evaluation of the implemented designs and the experimental validation of the eRTS estimations in both healthy and faulty scenarios. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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16 pages, 1560 KiB

Open AccessReview

Hardware-in-the-Loop and Digital Control Techniques Applied to Single-Phase PFC Converters

by Paula Lamo, Angel de Castro, Alberto Sanchez, Gustavo A. Ruiz, Francisco J. Azcondo and Alberto Pigazo

Electronics 2021, 10(13), 1563; https://doi.org/10.3390/electronics10131563 - 29 Jun 2021

Cited by 17 | Viewed by 4182

Abstract

Power electronic converters for power factor correction (PFC) play a key role in single-phase electrical power systems, ensuring that the line current waveform complies with the applicable standards and grid codes while regulating the DC voltage. Its verification implies significant complexity and cost, [...] Read more.

Power electronic converters for power factor correction (PFC) play a key role in single-phase electrical power systems, ensuring that the line current waveform complies with the applicable standards and grid codes while regulating the DC voltage. Its verification implies significant complexity and cost, since it requires long simulations to verify its behavior, for around hundreds of milliseconds. The development and test of the controller include nominal, abnormal and fault conditions in which the equipment could be damaged. Hardware-in-the-loop (HIL) is a cost-effective technique that allows the power converter to be replaced by a real-time simulation model, avoiding building prototypes in the early stages for the development and validation of the controller. However, the performance-vs-cost trade-off associated with HIL techniques depends on the mathematical models used for replicating the power converter, the load and the electrical grid, as well as the hardware platform chosen to build it, e.g., microprocessor or FPGA, and the required number of channels and I/O types to test the system. This work reviews state-of-the-art HIL techniques and digital control techniques for single-phase PFC converters. Full article

(This article belongs to the Special Issue Hardware in the Loop, Real-Time Simulation and Digital Control of Power Electronics and Drives)

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