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Micromachines
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Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications
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Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 31 December 2024 | Viewed by 3827

Special Issue Editors

Prof. Dr. Junshuai Xue

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Guest Editor
State Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology, School of Microelectronics, Xidian University, Xi'an 710017, China
Interests: GaN heterostructure; transition metal nitride electronic devices; GaN electronic devices
Dr. Xi Jiang

E-Mail Website
Guest Editor
State Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology, School of Microelectronics, Xidian University, Xi'an 710017, China
Interests: power semiconductor device; device reliability; power module package
Dr. Song Yuan

E-Mail Website
Guest Editor
State Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology, School of Microelectronics, Xidian University, Xi'an 710017, China
Interests: power semiconductor devices; wide-bandgap semiconductor devices; semiconductor device fabrication; semiconductor device reliability

Special Issue Information

Dear Colleagues,

Semiconductor devices play a pivotal role in modern electronics, facilitating the advancement of increasingly intricate and compact electronic systems. These systems are now ubiquitous across every facet of contemporary information society. In order to cater to diverse application requirements, modern semiconductor devices utilize a variety of materials, such as silicon (Si), gallium arsenide (GaAs), germanium (Ge), silicon carbide (SiC), and diamond. Moreover, there is a continual escalation in integration levels, accompanied by a corresponding increase in the complexity of fabrication processes. The principal factors shaping the trajectory of modern semiconductor device development include the intended application domains, the selection of materials for device fabrication, and the meticulous engineering of fabrication processes.

This Special Issue aims to provide a comprehensive overview of the latest advancements in emerging semiconductor devices, with a particular focus on the materials utilized, fabrication techniques employed, and the wide range of applications that these devices enable. Researchers and academics are invited to contribute original research papers and review articles that showcase innovative approaches and breakthroughs in the field of semiconductor devices, helping to pave the way for the next generation of electronic technologies.

Prof. Dr. Junshuai Xue
Dr. Xi Jiang
Dr. Song Yuan
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • wide-bandgap semiconductor materials and devices
  • power semiconductor devices
  • semiconductor performance characterization
  • power electronics
  • semiconductor device fabrication
  • semiconductor device reliability

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Published Papers (6 papers)

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Research

15 pages, 4459 KiB  
Article
Residual Stress and Warping Analysis of the Nano-Silver Pressureless Sintering Process in SiC Power Device Packaging
by Wenchao Tian, Dexin Li, Haojie Dang, Shiqian Liang, Yizheng Zhang, Xiaojun Zhang, Si Chen and Xiaochuan Yu
Micromachines 2024, 15(9), 1087; https://doi.org/10.3390/mi15091087 - 28 Aug 2024
Viewed by 418
Abstract
Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin–lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal [...] Read more.
Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin–lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal stress analysis of the nano-silver pressureless sintering process is more limited. In this study, the pressureless sintering process of nano-silver was studied using finite element software, with nano-silver as an interconnect material. Using the control variable method, we analyzed the influences of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices. In addition, orthogonal experiments were designed to optimize the parameters and determine the optimal combination of the process parameters. The results showed that the maximum residual stress of the module appeared on the connection surface between the power chip and the nano-silver solder paste layer. The module warping deformation was convex warping. The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wave change. Each parameter influenced the stress of the solder layer in this descending order: sintering temperature, cooling rate, solder paste area, and solder paste thickness. The residual stress of the nano-silver layer was 24.83 MPa under the optimal combination of the process parameters and was reduced by 29.38% compared with the original value of 35.162 MPa. Full article
(This article belongs to the Special Issue Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications)
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10 pages, 4456 KiB  
Article
A CMOS-Compatible Process for ≥3 kV GaN Power HEMTs on 6-inch Sapphire Using In Situ SiN as the Gate Dielectric
by Jie Zhang, Xiangdong Li, Jian Ji, Shuzhen You, Long Chen, Lezhi Wang, Zilan Li, Yue Hao and Jincheng Zhang
Micromachines 2024, 15(8), 1005; https://doi.org/10.3390/mi15081005 - 2 Aug 2024
Viewed by 706
Abstract
The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a [...] Read more.
The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a CMOS-compatible process. A 1.5 µm thin GaN buffer layer with excellent uniformity and a 20 nm in situ SiN gate dielectric ensured uniformly distributed VTH and RON across the entire 6-inch wafer. The fabricated devices with an LGD of 30 µm and WG of 36 mm exhibited an RON of 18.06 Ω·mm and an off-state breakdown voltage of over 3 kV. The electrical mapping visualizes the high uniformity of RON and VTH distributed across the whole 6-inch wafer, which is of great significance in promoting the applications of GaN power HEMTs for medium-voltage power electronics in the future. Full article
(This article belongs to the Special Issue Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications)
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12 pages, 4547 KiB  
Article
Study on Single Event Effects of Enhanced GaN HEMT Devices under Various Conditions
by Xinxiang Zhang, Yanrong Cao, Chuan Chen, Linshan Wu, Zhiheng Wang, Shuo Su, Weiwei Zhang, Ling Lv, Xuefeng Zheng, Wenchao Tian, Xiaohua Ma and Yue Hao
Micromachines 2024, 15(8), 950; https://doi.org/10.3390/mi15080950 - 24 Jul 2024
Viewed by 566
Abstract
GaN HEMT devices are sensitive to the single event effect (SEE) caused by heavy ions, and their reliability affects the safe use of space equipment. In this work, a Ge ion (LET = 37 MeV·cm2/mg) and Bi ion (LET = 98 [...] Read more.
GaN HEMT devices are sensitive to the single event effect (SEE) caused by heavy ions, and their reliability affects the safe use of space equipment. In this work, a Ge ion (LET = 37 MeV·cm2/mg) and Bi ion (LET = 98 MeV·cm2/mg) were used to irradiate Cascode GaN power devices by heavy ion accelerator experimental device. The differences of SEE under three conditions: pre-applied electrical stress, different LET values, and gate voltages are studied, and the related damage mechanism is discussed. The experimental results show that the pre-application of electrical stress before radiation leads to an electron de-trapping effect, generating defects within the GaN device. These defects will assist in charge collection so that the drain leakage current of the device will be enhanced. The higher the LET value, the more electron–hole pairs are ionized. Therefore, the charge collected by the drain increases, and the burn-out voltage advances. In the off state, the more negative the gate voltage, the higher the drain voltage of the GaN HEMT device, and the more serious the back-channel effect. This study provides an important theoretical basis for the reliability of GaN power devices in radiation environments. Full article
(This article belongs to the Special Issue Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications)
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16 pages, 506 KiB  
Article
Efficient Mixed-Type Wafer Defect Pattern Recognition Based on Light-Weight Neural Network
by Guangyuan Deng and Hongcheng Wang
Micromachines 2024, 15(7), 836; https://doi.org/10.3390/mi15070836 - 27 Jun 2024
Viewed by 581
Abstract
Wafer defect pattern recognition can help engineers improve the production process of semiconductor chips. In real industrial scenarios, the recognition of mixed-type wafer defects is difficult and the production scale of semiconductor wafers is large, which requires high accuracy and speed in wafer [...] Read more.
Wafer defect pattern recognition can help engineers improve the production process of semiconductor chips. In real industrial scenarios, the recognition of mixed-type wafer defects is difficult and the production scale of semiconductor wafers is large, which requires high accuracy and speed in wafer defect pattern recognition. This study proposes a light-weight neural network model to efficiently recognize mixed-type wafer defects. The proposed model is constructed via inverted residual convolution blocks with attention mechanisms and large kernel convolution downsampling layers. The inference speed of the inverted residual convolution block is fast, and the attention mechanism can enhance feature extraction capabilities. Large kernel convolutions help the network retain more important feature information during downsampling operations. The experimental results on the real Mixed-type WM38 dataset show that the proposed model achieves a recognition accuracy of 98.69% with only 1.01 M parameters. Compared with some popular high-performance models and light-weight models, our model has advantages in both recognition accuracy and inference speed. Finally, we deploy the model as a TensorRT engine, which significantly improves the inference speed of the model, enabling it to process more than 1300 wafer maps per second. Full article
(This article belongs to the Special Issue Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications)
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11 pages, 1913 KiB  
Article
Enhanced Hole Injection in AlGaN-Based Ga-Polar Ultraviolet Light-Emitting Diodes with Polarized Electric-Field Reservoir Electron Barrier
by Zhuang Zhao, Yang Liu, Peixian Li, Xiaowei Zhou, Bo Yang and Yingru Xiang
Micromachines 2024, 15(6), 762; https://doi.org/10.3390/mi15060762 - 6 Jun 2024
Viewed by 577
Abstract
In this study, we propose a polarized electron blocking layer (EBL) structure using AlxGa1−xN/AlxGa1−xN to enhance the internal quantum efficiency (IQE) of AlGaN-based ultraviolet light-emitting diodes (UV LEDs). Our findings indicate that this polarized EBL [...] Read more.
In this study, we propose a polarized electron blocking layer (EBL) structure using AlxGa1−xN/AlxGa1−xN to enhance the internal quantum efficiency (IQE) of AlGaN-based ultraviolet light-emitting diodes (UV LEDs). Our findings indicate that this polarized EBL structure significantly improves IQE compared to conventional EBLs. Additionally, we introduce an electric-field reservoir (EFR) optimization method to maximize IQE. Specifically, optimizing the polarized EBL structure of AlxGa1−xN/AlxGa1−xN enhances the hole drift rate, resulting in an IQE improvement of 19% and an optical output power increase of 186 mW at a current of 210 mA. Full article
(This article belongs to the Special Issue Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications)
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12 pages, 3610 KiB  
Article
A Novel IGBT with SIPOS Pillars Achieving Ultralow Power Loss in TCAD Simulation Study
by Song Yuan, Zhaoheng Yan, Yanzuo Li, Ying Wang, Qifan Liu, Xinbin Zhan, Xi Jiang, Yanjing He and Xiaowu Gong
Micromachines 2024, 15(6), 759; https://doi.org/10.3390/mi15060759 - 5 Jun 2024
Viewed by 556
Abstract
A novel insulated gate bipolar transistor with Semi-Insulated POly Silicon (SIPOS) is presented in this paper and analyzed through TCAD simulation. In the off state, the SIPOS-IGBT can obtain a uniform electric field distribution, which enables a thinner drift region under the same [...] Read more.
A novel insulated gate bipolar transistor with Semi-Insulated POly Silicon (SIPOS) is presented in this paper and analyzed through TCAD simulation. In the off state, the SIPOS-IGBT can obtain a uniform electric field distribution, which enables a thinner drift region under the same breakdown voltage. In the on state, an electron accumulation layer is formed along the SIPOS, which can increase the injection level of the “PiN region” in the device, and the carrier concentration in the drift region is also increased due to the charge balance effect. Moreover, the SIPOS-IGBT can achieve a quick and thorough depletion in the drift region during the turn-off transient, which can greatly reduce the turn-off loss of the SIPOS-IGBT. These advantages improve the tradeoff between the conduction and switching losses. According to the simulation results, the SIPOS-IGBT obtained a 58% lower turn loss than that of a field-stop (FS) IGBT and 30% lower than an HK-IGBT with the same on-state voltage. Full article
(This article belongs to the Special Issue Wide-Bandgap Semiconductor Devices: Materials, Fabrication, and Applications)
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