Search Results (76)

Intelligent sensing systems are increasingly used in wearable devices, enabling advanced tasks across various application domains including robotics and human–machine interaction. Ensuring these systems are energy autonomous is highly demanded, despite strict constraints on power, memory and processing resources. To meet these requirements, embedded neural networks must be optimized to achieve a balance between accuracy and efficiency. This paper presents an integrated approach that combines Hardware-Aware Neural Architecture Search (HW-NAS) with optimization techniques—weight reshaping, quantization, and their combination—to develop efficient classifiers for a multisensory glove. HW-NAS automatically derives 1D-CNN models tailored to the NUCLEO-F401RE board, while the additional optimization further reduces model size, memory usage, and latency. Across three datasets, the optimized models not only improve classification accuracy but also deliver an average reduction of 75% in inference time, 69% in flash memory, and more than 45% in RAM compared to NAS-only baselines. These results highlight the effectiveness of integrating NAS with optimization techniques, paving the way towards energy-autonomous wearable systems. Full article

To satisfy the superior surface quality requirements in the fabrication of HBM (High-Bandwidth Memory) and 3D NAND Flash Memory, high-efficiency Si chemical mechanical planarization (CMP) is essential. In this study, a colloidal silica abrasive-based Si-wafer CMP slurry was developed to simultaneously achieve a high polishing rate (≥10 nm/min) and low surface roughness (≤0.2 nm) without inducing CMP-induced scratches. The proposed Si-wafer CMP slurry incorporates two functional components: triammonium phosphate (TAP) as a hydrolysis reaction accelerator and hydroxyethyl cellulose (HEC) as an abrasive drag force accelerator. The polishing rate enhancement mechanism of TAP was analyzed by monitoring the OH⁻ mol concentration, surface adsorption behavior, and XPS spectra. The results showed that increasing the TAP concentration raised the OH⁻ mol concentration and converted Si–Si and Si–O–Si bonds to Si–OH via a hydrolysis reaction, thereby increasing the polishing rate. However, excessive hydrolysis also led to increased surface roughness. On the other hand, HEC influenced slurry viscosity, abrasive dispersibility, and drag force. At low HEC concentrations, increased abrasive drag force improved the polishing rate. At high concentrations, however, HEC formed a hindrance layer on the Si surface via hydrogen bonding and condensation reactions, reducing the effective contact area of abrasives and thus decreasing the polishing rate. By optimizing the concentrations of TAP (0.0037 wt%) and HEC (≤0.0024 wt%), the proposed slurry formulation achieved high-performance Si-wafer CMP, satisfying both surface roughness and polishing rate targets required for advanced memory packaging applications. Full article

Addressing the significant challenge of speech enhancement in ultra-low-Signal-to-Noise-Ratio (SNR) scenarios for Unmanned Aerial Vehicle (UAV) voice communication, particularly under edge deployment constraints, this study proposes the Edge-Deployed Band-Split Rotary Position Encoding Transformer (Edge-BS-RoFormer), a novel, lightweight band-split rotary position encoding transformer. While existing deep learning methods face limitations in dynamic UAV noise suppression under such constraints, including insufficient harmonic modeling and high computational complexity, the proposed Edge-BS-RoFormer distinctively synergizes a band-split strategy for fine-grained spectral processing, a dual-dimension Rotary Position Encoding ($\mathrm{RoPE}$) mechanism for superior joint time–frequency modeling, and $\mathrm{FlashAttention}$ to optimize computational efficiency, pivotal for its lightweight nature and robust ultra-low-SNR performance. Experiments on our self-constructed DroneNoise-LibriMix (DN-LM) dataset demonstrate Edge-BS-RoFormer’s superiority. Under a −15 dB SNR, it achieves Scale-Invariant Signal-to-Distortion Ratio (SI-SDR) improvements of 2.2 dB over Deep Complex U-Net (DCUNet), 25.0 dB over the Dual-Path Transformer Network (DPTNet), and 2.3 dB over HTDemucs. Correspondingly, the Perceptual Evaluation of Speech Quality (PESQ) is enhanced by 0.11, 0.18, and 0.15, respectively. Crucially, its efficacy for edge deployment is substantiated by a minimal model storage of 8.534 MB, 11.617 GFLOPs (an 89.6% reduction vs. DCUNet), a runtime memory footprint of under 500MB, a Real-Time Factor (RTF) of 0.325 (latency: 330.830 ms), and a power consumption of 6.536 W on an NVIDIA Jetson AGX Xavier, fulfilling real-time processing demands. This study delivers a validated lightweight solution, exemplified by its minimal computational overhead and real-time edge inference capability, for effective speech enhancement in complex UAV acoustic scenarios, including dynamic noise conditions. Furthermore, the open-sourced dataset and model contribute to advancing research and establishing standardized evaluation frameworks in this domain. Full article

In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were compared, confirming the linear behavior of short-channel devices due to velocity saturation. In the proposed system, analog WL voltages serve as inputs, and the summed bitline (BL) currents represent the outputs. Each synaptic weight is implemented using two paired devices, and each WL layer corresponds to a fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition is conducted, demonstrated only a 0.32% accuracy drop for the short-channel device compared to the ideal linear case, and 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight the strong potential of 3D-NAND flash memory, which offers high integration density and technological maturity, for neuromorphic computing applications. Full article

The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO₂/SiO_xN_y/SiO₂ (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability. Full article

This work investigates a new erase scheme in NAND flash memory to improve the lifetime and performance of modern solid-state drives (SSDs). In NAND flash memory, an erase operation applies a high voltage (e.g., >20 V) to flash cells for a long time (e.g., >3.5 ms), which degrades cell endurance and potentially delays user I/O requests. While a large body of prior work has proposed various techniques to mitigate the negative impact of erase operations, no work has yet investigated how erase latency and voltage should be set to fully exploit the potential of NAND flash memory; most existing techniques use a fixed latency and voltage for every erase operation, which is set to cover the worst-case operating conditions. To address this, we propose Revisiting Erase Operation, (REO) a new erase scheme that dynamically adjusts erase latency and voltage depending on the cells’ current erase characteristics. We design REO by two key apporaches. First, REO accurately predicts such near-optimal erase latency based on the number of fail bits during an erase operation. To maximize its benefits, REO aggressively yet safely reduces erase latency by leveraging a large reliability margin present in modern SSDs. Second, REO applies near-optimal erase voltage to each WL based on its unique erase characteristics. We demonstrate the feasibility and reliability of REO using 160 real 3D NAND flash chips, showing that it enhances SSD lifetime over the conventional erase scheme by 43% without change to existing NAND flash chips. Our system-level evaluation using eleven real-world workloads shows that an REO-enabled SSD reduces average I/O performance and read tail latency by 12% and 38%, respectivley, on average over a state-of-the-art technique. Full article

The impacts of total ionizing dose (TID) were investigated in 28 nm 3D charge trapping (CT) NAND Flash memories. This study focused on the variations in the raw bit error rate (RBER) of irradiated flash across different operational modes and bias states. It was observed that the data pattern stored in Flash influences the bit error count after irradiation. The experimental findings demonstrated a dose-dependent relationship with standby current, read operation current, and threshold voltage shifts. Additionally, TID was found to affect the time required for erasure and programming operations. These results were then bench-marked against similar NAND Flash devices, revealing superior resistance to TID effects. Full article

Crop damage attributed to pest birds is an important problem, particularly in low-income countries. This paper describes a prototype system for pest bird detection using a Conv1D neural network model followed by scaring actions to reduce the presence of pest birds on farms. Acoustic recorders were deployed on farms for data collection, supplemented by acoustic libraries. The sounds of pest bird species were identified and labeled. The labeled data were used in Edge Impulse to train a tinyML Conv1D model to detect birds of interest. The model was deployed on Arduino Nano 33 BLE Sense (nodes) and XIAO (Base station) microcontrollers to detect the pest birds, and based on the detection, scaring sounds were played to deter the birds. The model achieved an accuracy of 96.1% during training and 92.99% during testing. The testing F1 score was 0.94, and the ROC score was 0.99, signifying a good discriminatory ability of the model. The prototype was able to make inferences in 53 ms using only 14.8 k of peak RAM and only 43.8 K of flash memory to store the model. Results from the prototype deployment in the field demonstrated successful detection and triggering actions and SMS messaging notifications. Further development of this novel integrated and sustainable solution will add another tool for dealing with pest birds. Full article

Diabetes is a chronic condition, and traditional monitoring methods are invasive, significantly reducing the quality of life of the patients. This study proposes the design of an innovative system based on a microcontroller that performs real-time ECG acquisition and evaluates the presence of diabetes using an Edge-AI solution. A spectrogram-based preprocessing method is combined with a 1-Dimensional Convolutional Neural Network (1D-CNN) to analyze the ECG signals directly on the device. By applying quantization as an optimization technique, the model effectively balances memory usage and accuracy, achieving an accuracy of 89.52% with an average precision and recall of 0.91 and 0.90, respectively. These results were obtained with a minimal memory footprint of 347 kB flash and 23 kB RAM, showcasing the system’s suitability for wearable embedded devices. Furthermore, a custom PCB was developed to validate the system in a real-world scenario. The hardware integrates high-performance electronics with low power consumption, demonstrating the feasibility of deploying Edge-AI for non-invasive, real-time diabetes detection in resource-constrained environments. This design represents a significant step forward in improving the accessibility and practicality of diabetes monitoring. Full article

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase. Modeling results for the GIDL-assisted Erase operation, finally, allow not only to support this conclusion but also to directly correlate the change with temperature of the electrostatic potential of the string body with the change with temperature of the erased threshold-voltage of the memory cells. Full article

To successfully meet the various requirements of modern storage systems, NAND flash memory should be highly optimized by precisely tuning a huge number of internal operating parameters. Although 3D NAND flash memory succeeds in increasing the capacity of storage systems, its complex architecture and unique error behavior make such optimization a more difficult and time-consuming process during NAND manufacturing. In this paper, we introduce HAIPO, a novel methodology for post-fabrication optimization of NAND flash memory, which is an essential step in the manufacturing process of modern 3D NAND flash memory to simultaneously meet various requirements on reliability, performance, yield, etc. HAIPO is based on simple machine-learning approaches that consist of (i) a lightweight deep-learning (DL) model to generate initial device parameters and (ii) an evolutionary algorithm (EA) to explore device parameters automatically. To more effectively explore device parameters, we introduce three key guidelines for each generation in the EA: (1) domain-specific rules, (2) recent optimization results, and (3) online Bayesian simulation, respectively, to enable quick optimization for a huge number of device parameters within the limited product turnaround time (TAT). In addition, we integrate two optimization modules with HAIPO to improve optimization efficiency even in environments with severe process variation. We demonstrate the feasibility and effectiveness of HAIPO using real 320 3D TLC/QLC NAND flash chips, showing significant performance and reliability improvements by up to 8.8% and 12% on average, respectively, within a quite limited optimization TAT. Full article

With vertical stacking, 3D NAND’s flash memory can achieve continuous capacity growth. However, the endurance variation between the stacked layers becomes more and more significant due to process variation, which will lead to the underutilization of many pages and seriously affect the lifetime of 3D NAND’s flash memory. We investigated the endurance variation characteristics between layers and divided the stacked layers into the top, middle, and bottom layers according to the endurance characteristics. We found that the endurance of the bottom layer pages is much weaker than that of the other two layers, which is the primary factor that affects the lifetime of 3D NAND’s flash memory. In response to this endurance variation feature, we proposed a new layer-aware write strategy, called LA-Write. First of all, the write–skip unit in LA-Write will reduce the wear pressure of the pages through write–skip operations. Secondly, LA-Write maintains a layer-aware table, which stores the probability of pages in different layers performing the write–skip operation. Setting the probability of the bottom pages to the highest value will result in more write–skip operations on the bottom layers, mitigating endurance variations between layers. We carried out our experiments of LA-Write on DiskSim, a popular SSD simulator. Compared to existing schemes, experimental results show that LA-Write can greatly increase SSD’s lifetime. Full article

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string. Full article

Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems. Full article

Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory. Full article