Search Results (55)

The fully depleted silicon on insulator (FDSOI) integrated circuit process has a buried oxygen layer in its structure, which provides many advantages to the FDSOI integrated circuit process, such as isolating the substrate from the conductive channel, reducing leakage current, and lowering the supply voltage. With the vigorous development of space artificial intelligence infrastructure in China and the United States, it is becoming increasingly important to study the single-event upset (SEU) of Static Random-Access Memory (SRAM) cells caused by particle radiation. In this paper, SRAM with different peripheral circuits is designed by domestically produced 22 nm FDSOI CMOS integrated circuit technology. Simulations are used to study the mechanism of single-event effects for SRAM, and single-particle radiation experiments of Kr are used to characterize SEU for SRAM. The results showed that the SRAM without Error Detection and Correction (EDAC) technology had 6486 cell upsets, with incidences of 2-cell upsets occurring 15 times, and no multi-cell flips occurred. For the SRAM using EDAC technology, there was no single-cell upset, 430 incidences of two-cell upsets and one incidence of multi-cell upsets. This provides strong support for fully utilizing EDAC technology to enhance the irradiation-hardening of digital integrated circuits. For metal oxide semiconductor field-effect transistors, the source and drain structures are completely symmetrical, and when in use, they are only connected at different potentials. Full article

This paper presents a frequency-reconfigurable dual-band phase shifter operating in the n257 (26.5–29.5 GHz) and n260 (37–40 GHz) bands for fifth-generation (5G) communication. The proposed phase shifter is based on an active vector-summing architecture and provides simultaneous gain and phase control for beamforming applications. To support dual-band operation with a large frequency separation, a reconfigurable RC–RL polyphase filter (PPF) is employed for in-phase/quadrature (I/Q) signal generation. The proposed PPF reconfigures its inductance and capacitance according to the operating band, reducing insertion loss and minimizing I/Q phase error in both frequency bands. Gain and phase are controlled by digital-to-analog converter (DAC)-assisted vector summation with 4-bit gain and 6-bit phase control resolution, while a reconfigurable output matching network provides optimized impedance matching in each operating mode. The phase shifter is implemented in a 28 nm fully depleted silicon-on-insulator (FDSOI) process with a core area of 0.26 mm². The measured RMS phase errors are <1.18° and <1.5°, and the RMS gain errors are <0.26 dB and <0.35 dB in the n257 and n260 bands, respectively. The measured DC power consumption is 11 mW and 15.4 mW in the n257 and n260 bands, respectively. Full article

Hafnium-zirconium oxide (HZO)-based ferroelectric field-effect transistors (FeFETs) are expected to become core devices for new embedded memory and compute-in-memory systems. However, existing simulations rely on finite-element-based TCAD tools, which are computationally intensive and time-consuming, and they struggle to account for the dynamic flipping of ferroelectric domains. This paper utilizes a time-domain simulation framework based on the nucleation-limited switching (NLS) model coupled with the surface potential of a MOSFET, enabling a self-consistent solution for polarization and electrical characteristics; a Monte Carlo method is employed to simulate device variability, and Shmoo plots are used to identify optimal programming and erasure process windows; an integrated solution is proposed for 22 nm FDSOI devices, addressing geometric scaling, modification of the Landau–Khalatnikov (L-K) dynamic model for ultrathin ferroelectric layers, and suppression of short-channel effects. Model validation is limited to selected operating metrics, and predictive accuracy outside the calibrated cases requires additional independent datasets. This method enables end-to-end simulation of FeFETs, from material polarization and device electrical characteristics to performance optimization, thereby providing model-based analytical and design support for the development of advanced, ultra-low-power FeFETs. Full article

This paper presents a radiation-hardened 4-bit flash analog-to-digital converter (ADC) implemented in a 22 nm fully depleted silicon-on-insulator (FD-SOI) process for high-reliability applications in radiation environments. To improve single-event upsets (SEU) tolerance, the design introduces a compact fault-tolerant logic scheme based on Dual Modular Redundancy (DMR), offering reliability comparable to Triple Modular Redundancy (TMR) while using two storage nodes instead of three, and a simple XOR-based check in place of a majority voter. A distributed sampling architecture mitigates SEU vulnerabilities in the input path, while thin-oxide devices are used in analog-critical circuits to enhance total ionizing dose (TID) resilience. Post-layout simulations demonstrate SEU detection within 200 ps and correction within ~600 ps. The ADC achieves an active area of 0.089 mm², power consumption below 30 µW, and provides a scalable solution for radiation-tolerant data acquisition in aerospace and other high-reliability systems. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz. Full article

Millimeter-wave (mm-Wave) phased array systems need to meet the transmitter (Tx) equivalent isotropic radiated power (EIRP) requirement, and that depends mainly on the design of two key sub-components: (1) the antenna array and (2) the Tx power amplifier (PA) in the front-end-modules (FEMs). Simulations using an electromagnetic (EM) solver carried out in Cadence AWR with AXIEM suggest that for two uniform square patch antenna arrays at 24 GHz, the 4 element array has ~6 dB lower antenna gain and twice the half power beam width (HPBW) compared to the 16 element array. We also present measurements and post-layout parasitic-extracted (PEX) EM simulation data taken on two broadband mm-Wave PAs designed in our lab that cover the key portions of the fifth-generation (5G) FR2-band (i.e., 24.25–52.6 GHz) that lies between the super-high-frequency (SHF, i.e., 3–30 GHz) band and the extremely-high-frequency (EHF, i.e., 30–300 GHz) band: one designed in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS process, and the other in an advanced 40 nm Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) process. The FD-SOI PA achieves saturated output power (P_OUT,SAT) of ~14 dBm and peak power-added efficiency (PAE) of ~20% with ~14 dB of gain and 3 dB bandwidth (BW) from ~19.1 to 46.5 GHz in measurement, while the GaN PA achieves measured P_OUT,SAT of ~24 dBm and peak PAE of ~20% with ~20 dB gain and 3 dB BW from ~19.9 to 35.2 GHz. The PAs’ measured data are in good agreement with the PEX EM simulated data, and 3rd Watt-level GaN PA design data are also presented, but with simulated PEX EM data only. Assuming each antenna element will be driven by one FEM and each phased array targets the same 65 dBm EIRP, millimeter wave (mm-Wave) antenna arrays using the Watt-level GaN PAs and FEMs are expected to achieve roughly 2× wider HPBW with 4× reduction in the array size compared with the arrays using Si FEMs, which shall alleviate the thorny mm-Wave line-of-sight (LOS)-blocking problems significantly. Full article

In this paper, the degradation mechanism of the RF performance of 22 nm fully depleted (FD) silicon-on-insulator nMOSFETs at different total ionizing dose levels has been investigated. The RF figures of merit (the cut-off frequency f_T, maximum oscillation frequency f_max) show significant degradation of approximately 14.1% and 6.8%, respectively. The variation of the small-signal parameters (output conductance (g_ds), transconductance (g_m), reflection coefficient (|Γ_in|), and capacitance (C_gg)) at different TID levels has been discussed. TID-induced trapped charges in the gate oxide and buried oxide increase the vertical channel field, which leads to more complex degradation of small-signal parameters across a wide frequency range. Full article

In this paper, we propose a cost-effective way to tune RF process technology to achieve well-optimized RF and mmWave performances/power/area by tweaking back-end-of-line (BEOL) configurations. This paper suggests that the most favorable altitude is that of an ultra-thick-metal (UTM) layer from the silicon substrate, and the effort also focuses on the calibration of the via height/pitch underneath the UTM to satisfy the least ohmic loss in the interface between the active and passive device components. We implemented a process optimization in a 28 nm fully depleted silicon-on-insulator (FD-SOI) process technology, and the results show performance enhancements on the inductor, achieving a 14.8% quality factor improvement and a 13.1% self-resonance frequency improvement. This paper also showcases how the process optimization boosts 29 GHz LNA performances, with a 31.8% gain in boosting and a 9.1% reduction in noise-figure. Full article

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR). Full article

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology. Full article

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation. Full article

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm². Full article

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (P_DC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S₂₁-3 dB-BW [GHz])/(P_DC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. Full article

D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the value stored in the flip-flop. On this basis, a new structure D flip-flop is proposed in this paper. This flip-flop uses an asymmetric scheme in which the master–slave latch adopts different hardening structures. By sacrificing circuit speed in exchange for stronger SEU fortification capability, the SEU threshold of this structure is improved by 10 times compared to traditional D flip-flops. It has also been compared with Dual Interlocked Storage Elements (DICEs), and it saves the area cost of six transistors compared to the DICE structure. Under the same operating conditions, the average power consumption and peak power consumption are, respectively, 9.8% and 18.8% lower than those of the DICE circuit, making it suitable for soft radiation environments where high circuit speed is not a critical requirement. Full article