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J. Low Power Electron. Appl., Volume 7, Issue 3 (September 2017)

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Editorial

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Open AccessEditorial A Summary of the Special Issue “Emerging Network-on-Chip Architectures for Low Power Embedded Systems”
J. Low Power Electron. Appl. 2017, 7(3), 18; doi:10.3390/jlpea7030018
Received: 20 June 2017 / Revised: 26 June 2017 / Accepted: 26 June 2017 / Published: 29 June 2017
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(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)

Research

Jump to: Editorial

Open AccessArticle Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing
J. Low Power Electron. Appl. 2017, 7(3), 17; doi:10.3390/jlpea7030017
Received: 24 April 2017 / Revised: 20 June 2017 / Accepted: 20 June 2017 / Published: 27 June 2017
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Abstract
The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer
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The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle Characterization of an ISFET with Built-in Calibration Registers through Segmented Eight-Bit Binary Search in Three-Point Algorithm Using FPGA
J. Low Power Electron. Appl. 2017, 7(3), 19; doi:10.3390/jlpea7030019
Received: 31 May 2017 / Revised: 10 July 2017 / Accepted: 11 July 2017 / Published: 13 July 2017
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Abstract
Sensors play the most important role in observing changes in an environment they are a part. They detect even the smallest changes and send the information to other electronic devices. Making sure that these sensors provide an accurate output is equally crucial, as
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Sensors play the most important role in observing changes in an environment they are a part. They detect even the smallest changes and send the information to other electronic devices. Making sure that these sensors provide an accurate output is equally crucial, as the data it measures and collects are used for analysis. Until now, calibrating sensors has been done manually by following a sequence of procedures, and is usually performed on-site or in a laboratory prior to deployment. To eliminate the manual procedure in the calibration (at the very least), an ion-sensitive field-effect transistor (ISFET) with a built-in calibration registers circuit was created through segmented eight-bit binary search in a three-point algorithm using a field-programmable gate array (FPGA). The circuit was created using a three-point calibration algorithm and three standard buffers (pH 4, pH 7, and pH 10). The block diagram, schematic diagram, and the number of logic gates were derived after synthesizing the Verilog program in Xilinx/FPGA. An average of 0.30% error was computed to prove the reliability of the created circuit using FPGA. Having an ISFET with built-in calibration registers will alleviate the work of experts in performing calibrations. This would follow the plug and play standard, hence its being a calibration-ready ISFET device. With this feature, it could be used as a pH level meter or a remote sensor node in several applications. Full article
(This article belongs to the Special Issue Selected Papers from IEEE ISOCC Conference 2016)
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Open AccessArticle Ultra-Low Power Consuming Direct Radiation Sensors Based on Floating Gate Structures
J. Low Power Electron. Appl. 2017, 7(3), 20; doi:10.3390/jlpea7030020
Received: 21 June 2017 / Revised: 23 July 2017 / Accepted: 28 July 2017 / Published: 31 July 2017
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Abstract
In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail.
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In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions) was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle Models and Techniques for Temperature Robust Systems on a Reconfigurable Platform
J. Low Power Electron. Appl. 2017, 7(3), 21; doi:10.3390/jlpea7030021
Received: 31 July 2017 / Revised: 21 August 2017 / Accepted: 26 August 2017 / Published: 30 August 2017
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Abstract
This paper investigates the variability of various circuits and systems over temperature and presents several methods to improve their performance over temperature. The work demonstrates use of large scale reconfigurable System-On-Chip (SOC) for reducing the variability of circuits and systems compiled on a
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This paper investigates the variability of various circuits and systems over temperature and presents several methods to improve their performance over temperature. The work demonstrates use of large scale reconfigurable System-On-Chip (SOC) for reducing the variability of circuits and systems compiled on a Floating Gate (FG) based Field Programmable Analog Array (FPAA). Temperature dependencies of circuits are modeled using an open-source simulator built in the Scilab/XCOS environment and the results are compared with measurement data obtained from the FPAA. This comparison gives further insight into the temperature dependence of various circuits and signal processing systems and allows us to compensate as well as predict their behavior. Also, the work presents several different current and voltage references that could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment that could be easily compiled on the FPAA. An FG based current reference is then used for biasing a 12 × 1 Vector Matrix Multiplication (VMM) circuit and a second order G m C bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large scale FG FPAA presented here is fabricated in a 350 nm CMOS process. Full article
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Open AccessArticle Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators
J. Low Power Electron. Appl. 2017, 7(3), 22; doi:10.3390/jlpea7030022
Received: 10 July 2017 / Revised: 14 August 2017 / Accepted: 23 August 2017 / Published: 6 September 2017
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Abstract
It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While
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It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below. Full article
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Open AccessArticle DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability
J. Low Power Electron. Appl. 2017, 7(3), 23; doi:10.3390/jlpea7030023
Received: 2 August 2017 / Revised: 29 August 2017 / Accepted: 4 September 2017 / Published: 11 September 2017
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Abstract
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies,
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To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications
J. Low Power Electron. Appl. 2017, 7(3), 24; doi:10.3390/jlpea7030024
Received: 2 August 2017 / Revised: 5 September 2017 / Accepted: 13 September 2017 / Published: 20 September 2017
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Abstract
In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic
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In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high static and dynamic noise margins. The IoT application requires battery-enabled low leakage memory architecture in a subthreshold regime. Therefore, to improve leakage power consumption and provide better cell stability, a power-gated robust 10T SRAM is presented in this paper. The proposed cell uses a power-gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the stacking of n-MOS transistors in 10T SRAM latch and by separating the read path from the 10T SRAM latch, the static and dynamic noise margins in read and write operations has shown significant tolerance w.r.t. the variations in device process, voltage, and temperature (PVT) values. The proposed SRAM shows significantly improved performance in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write ability or write trip point (WTP), read–write energy, and dynamic read margin (DRM). Furthermore, these parameters of the proposed cell are observed at 8-Kilo bit (Kb) SRAM and compared with existing SRAM architectures. From the Monte Carlo simulation results, it is observed that the leakage power of a proposed low threshold voltage-LVT 10T SRAM is reduced by 98.76%, 98.6%, 6.7%, and 98.2% as compared to the LVT C6T, RD8T, LP9T, and ST10T SRAM, respectively, at 0.3V VDD. Additionally, in the proposed 10T SRAM, parameters such as RSNM, WSNM, WTP, and DRM are improved by 3×, 2×, 1.11×, and 1.32×, respectively, as compared to C6T SRAM. Similarly, the proposed 10T SRAM shows an improvement of 1.48×, 1.25×, and 1.1× in RSNM, WSNM, and WTP, respectively, in the parameters as compared to RD8T SRAM at 0.3 V VDD. Full article
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