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Micromachines
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Reliability Issues in Advanced Transistor Nodes
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Reliability Issues in Advanced Transistor Nodes

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: 30 May 2024 | Viewed by 7909

Special Issue Editor

Dr. Stanislav Tyaginov

E-Mail Website
Guest Editor
Interuniversity Microelectronics Centre (IMEC), 3001 Leuven, Belgium
Interests: transistor reliability; device and degradation modeling; hot-carrier degradation; bias temperature instability; time dependent dielectric breakdown; 2D materials; SiC; tunneling phenomena

Special Issue Information

Dear Colleagues,

Microelectronics, based on metal-oxide-semiconductor field effect transistors (MOSFETs), pervade all aspects of our lives and enable progress in virtually all fields. Although transistor scaling has been actively exploited for more than 50 years, MOSFET technology still has another 10–15 years’ worth of progression left to undergo. To enable further progress in mobile electronic components and gadgets, novel transistor architectures, such as fin, nanowire, nanosheet, forksheet, and complementary FET structures, have recently been introduced. These advanced transistor nodes are designed to ensure low OFF currents and long battery life.     

However, any further developments and progress can only be achieved by acquiring and retaining a thorough understanding of the microscopic physics underlying the behavior of novel devices and materials. Unlike the more tangible product parameters, such as performance or power consumption, reliability specifications are often neither disclosed nor considered by the typical end-user. In practice, however, reliability is the essential metric required for the introduction of each new transistor node. Accordingly, this Special Issue seeks to showcase research papers and review articles that focus on the most detrimental reliability concerns plaguing modern transistors, such as hot-carrier degradation, self-heating, bias–temperature instability, OFF-state stress, and time-dependent dielectric breakdown. Special attention will be paid to (i) experimental studies/characterization and (ii) modeling of these degradation mechanisms, as well as on (iii) pathways to device architecture optimization targeting alleviation of these parasitic effects.

We look forward to receiving your submissions.

Dr. Stanislav Tyaginov
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • reliability issues
  • hot-carrier degradation
  • self-heating
  • bias temperature instability
  • time-dependent dielectric breakdown
  • defects
  • characterization of reliability issues
  • modeling of reliability issues
  • novel transistor architectures
  • finFET
  • NWFET
  • NSFET
  • FSFET
  • CFET

Published Papers (8 papers)

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Research

Jump to: Review

10 pages, 2955 KiB  
Article
On the Aging of OTFTs and Its Impact on PUFs Reliability
by Marc Porti, Gerard Palau, Albert Crespo-Yepes, August Arnal Rus, Simon Ogier, Eloi Ramon and Montserrat Nafria
Micromachines 2024, 15(4), 443; https://doi.org/10.3390/mi15040443 - 26 Mar 2024
Viewed by 479
Abstract
Given the current maturity of printed technologies, Organic Thin-Film Transistors (OTFT) still show high initial variability, which can be beneficial for its exploitation in security applications. In this work, the process-related variability and aging of commercial OTFTs have been characterized to evaluate the [...] Read more.
Given the current maturity of printed technologies, Organic Thin-Film Transistors (OTFT) still show high initial variability, which can be beneficial for its exploitation in security applications. In this work, the process-related variability and aging of commercial OTFTs have been characterized to evaluate the feasibility of OTFTs-based Physical Unclonable Functions (PUFs) implementation. For our devices, ID-based PUFs show good uniformity and uniqueness. However, PUFs’ reliability could be compromised because of the observed transient and aging effects in the OTFTs, which could hinder the reproducibility of the generated fingerprints. A systematic study of the aging of OTFTs has been performed to evaluate the PUFs’ reliability. Our results suggest that the observed transient and aging effects could be mitigated so that the OTFTs-based PUFs’ reliability could be improved. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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13 pages, 3850 KiB  
Article
Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors
by Xiaoming Li, Yali Shao, Yunqi Wang, Fang Liu, Fengyu Kuang, Yiqi Zhuang and Cong Li
Micromachines 2024, 15(3), 420; https://doi.org/10.3390/mi15030420 - 21 Mar 2024
Viewed by 868
Abstract
In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the [...] Read more.
In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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13 pages, 2326 KiB  
Article
RC-Effects on the Oxide of SOI MOSFET under Off-State TDDB Degradation: RF Characterization and Modeling
by Alan Otero-Carrascal, Dora Chaparro-Ortiz, Purushothaman Srinivasan, Oscar Huerta, Edmundo Gutiérrez-Domínguez and Reydezel Torres-Torres
Micromachines 2024, 15(2), 252; https://doi.org/10.3390/mi15020252 - 07 Feb 2024
Viewed by 710
Abstract
Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. [...] Read more.
Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device’s impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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11 pages, 3062 KiB  
Article
Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling
by Alain Bravaix, Hugo Pitard, Xavier Federspiel and Florian Cacho
Micromachines 2024, 15(2), 205; https://doi.org/10.3390/mi15020205 - 30 Jan 2024
Viewed by 683
Abstract
A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (V [...] Read more.
A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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11 pages, 2518 KiB  
Article
Ultrathin Flexible Encapsulation Materials Based on Al2O3/Alucone Nanolaminates for Improved Electrical Stability of Silicon Nanomembrane-Based MOS Capacitors
by Zhuofan Wang, Hongliang Lu, Yuming Zhang, Chen Liu, Haonan Zhang and Yanhao Yu
Micromachines 2024, 15(1), 41; https://doi.org/10.3390/mi15010041 - 24 Dec 2023
Viewed by 985
Abstract
Ultrathin flexible encapsulation (UFE) using multilayered films has prospects for practical applications, such as implantable and wearable electronics. However, existing investigations of the effect of mechanical bending strains on electrical properties after the encapsulation procedure provide insufficient information for improving the electrical stability [...] Read more.
Ultrathin flexible encapsulation (UFE) using multilayered films has prospects for practical applications, such as implantable and wearable electronics. However, existing investigations of the effect of mechanical bending strains on electrical properties after the encapsulation procedure provide insufficient information for improving the electrical stability of ultrathin silicon nanomembrane (Si NM)-based metal oxide semiconductor capacitors (MOSCAPs). Here, we used atomic layer deposition and molecular layer deposition to generate 3.5 dyads of alternating 11 nm Al2O3 and 3.5 nm aluminum alkoxide (alucone) nanolaminates on flexible Si NM-based MOSCAPs. Moreover, we bent the MOSCAPs inwardly to radii of 85 and 110.5 mm and outwardly to radii of 77.5 and 38.5 mm. Subsequently, we tested the unbent and bent MOSCAPs to determine the effect of strain on various electrical parameters, namely the maximum capacitance, minimum capacitance, gate leakage current density, hysteresis voltage, effective oxide charge, oxide trapped charge, interface trap density, and frequency dispersion. The comparison of encapsulated and unencapsulated MOSCAPs on these critical parameters at bending strains indicated that Al2O3/alucone nanolaminates stabilized the electrical and interfacial characteristics of the Si NM-based MOSCAPs. These results highlight that ultrathin Al2O3/alucone nanolaminates are promising encapsulation materials for prolonging the operational lifetimes of flexible Si NM-based metal oxide semiconductor field-effect transistors. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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23 pages, 24626 KiB  
Article
Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs
by Stanislav Tyaginov, Barry O’Sullivan, Adrian Chasin, Yaksh Rawal, Thomas Chiarella, Camila Toledo de Carvalho Cavalcante, Yosuke Kimura, Michiel Vandemaele, Romain Ritzenthaler, Jerome Mitard, Senthil Vadakupudhu Palayam, Jason Reifsnider and Ben Kaczer
Micromachines 2023, 14(8), 1514; https://doi.org/10.3390/mi14081514 - 28 Jul 2023
Cited by 3 | Viewed by 1149
Abstract
We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel [...] Read more.
We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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Review

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20 pages, 8766 KiB  
Review
A Review of Reliability in Gate-All-Around Nanosheet Devices
by Miaomiao Wang
Micromachines 2024, 15(2), 269; https://doi.org/10.3390/mi15020269 - 13 Feb 2024
Viewed by 1247
Abstract
The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, [...] Read more.
The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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21 pages, 6141 KiB  
Review
The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms
by Zixuan Sun, Sihao Chen, Lining Zhang, Ru Huang and Runsheng Wang
Micromachines 2024, 15(1), 127; https://doi.org/10.3390/mi15010127 - 12 Jan 2024
Cited by 1 | Viewed by 1137
Abstract
With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode [...] Read more.
With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)
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