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Micromachines
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Nanoscale Switches
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Nanoscale Switches

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (28 February 2019) | Viewed by 16598

Special Issue Editor

Prof. Dr. Doo Seok Jeong

E-Mail Website
Guest Editor
Division of Materials Science and Engineering, Hanyang University, Wansimni-ro 222, Seongdong-gu, Seoul 04763, Republic of Korea
Interests: nonvolatile switch; neuromorphic engineering; spiking neural network; learning algorithm

Special Issue Information

Dear Colleagues,

Nanoscale switches refer to volatile or nonvolatile resistance switches that can potentially be reduced down to the nanometer scale with regard to their working principles. They include transition metal oxide-based valence change memory, phase-change memory, ferroelectric tunnel junction, ferromagnetic tunnel junction, and so forth. Such nanoscale switches offer promising solutions to high-density and large-scale nonvolatile random access memory in the digital computing framework. Moreover, when formed in a passive crossbar array, the switches inherently support multiply-accumulate operation with ideally minimum time complexity, which is the heart of nonvolatile memory-based neuromorphic computing. Nanoscale switches are important ingredients of emerging technologies other than these examples, offering opportunities to overcome the critical issues encountered by the mainstream memory and logic technologies. Nevertheless, there remain challenges to overcome in order for these forward-looking technologies to become alternatives to the current technologies. Given such importance of nanoscale switches, we offer this Special Issue on “Nanoscale Switches”, which will encompass (1) original research articles on topics from fundamentals to nonvolatile memory or neumorphic computing applications of various classes of nanoscale switches and (2) insightful review papers.

Prof. Doo Seok Jeong
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Resistive switching memory
  • Valence-change memory
  • Memristor
  • Phase-change memory
  • Ferroelectric tunnel junction
  • Magnetic tunnel junction
  • Multiferroic tunnel junction
  • Threshold (volatile) switching
  • Neuromorphic computing
  • Learning algorithm

Published Papers (5 papers)

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Research

9 pages, 2166 KiB  
Article
Effect of Electrode Material on the Crystallization of GeTe Grown by Atomic Layer Deposition for Phase Change Random Access Memory
by Seung Ik Oh, In Hyuk Im, Chanyoung Yoo, Sung Yeon Ryu, Yong Kim, Seok Choi, Taeyong Eom, Cheol Seong Hwang and Byung Joon Choi
Micromachines 2019, 10(5), 281; https://doi.org/10.3390/mi10050281 - 27 Apr 2019
Cited by 9 | Viewed by 3013
Abstract
The electrical switching behavior of the GeTe phase-changing material grown by atomic layer deposition is characterized for the phase change random access memory (PCRAM) application. Planar-type PCRAM devices are fabricated with a TiN or W bottom electrode (BE). The crystallization behavior is characterized [...] Read more.
The electrical switching behavior of the GeTe phase-changing material grown by atomic layer deposition is characterized for the phase change random access memory (PCRAM) application. Planar-type PCRAM devices are fabricated with a TiN or W bottom electrode (BE). The crystallization behavior is characterized by applying an electrical pulse train and analyzed by applying the Johnson–Mehl–Avrami kinetics model. The device with TiN BE shows a high Avrami coefficient (>4), meaning that continuous and multiple nucleations occur during crystallization (set switching). Meanwhile, the device with W BE shows a smaller Avrami coefficient (~3), representing retarded nucleation during the crystallization. In addition, larger voltage and power are necessary for crystallization in case of the device with W BE. It is believed that the thermal conductivity of the BE material affects the temperature distribution in the device, resulting in different crystallization kinetics and set switching behavior. Full article
(This article belongs to the Special Issue Nanoscale Switches)
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18 pages, 2699 KiB  
Article
Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
by Khoa Van Pham, Tien Van Nguyen and Kyeong-Sik Min
Micromachines 2019, 10(4), 245; https://doi.org/10.3390/mi10040245 - 13 Apr 2019
Cited by 12 | Viewed by 3202
Abstract
A real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programming the [...] Read more.
A real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programming the memristors takes a very long time and consumes a large amount of power, because of the incremental behavior of memristor’s program-verify scheme for the fine-tuning of memristor’s conductance. To reduce the programming time and power, the partial gating scheme is proposed here to realize the partial training, where only some part of neurons are trained, which are more responsible in the recognition error. By retraining the part, rather than the entire crossbar, the programming time and power of memristor crossbar can be significantly reduced. The proposed scheme has been verified by CADENCE circuit simulation with the real memristor’s Verilog-A model. When compared to retraining the entire crossbar, the loss of recognition rate of the partial gating scheme has been estimated only as small as 2.5% and 2.9%, for the MNIST and CIFAR-10 datasets, respectively. However, the programming time and power can be saved by 86% and 89.5% than the 100% retraining, respectively. Full article
(This article belongs to the Special Issue Nanoscale Switches)
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8 pages, 1912 KiB  
Article
Artificial Neural Network for Response Inference of a Nonvolatile Resistance-Switch Array
by Guhyun Kim, Vladimir Kornijcuk, Dohun Kim, Inho Kim, Cheol Seong Hwang and Doo Seok Jeong
Micromachines 2019, 10(4), 219; https://doi.org/10.3390/mi10040219 - 27 Mar 2019
Cited by 3 | Viewed by 2918
Abstract
An artificial neural network was utilized in the behavior inference of a random crossbar array (10 × 9 or 28 × 27 in size) of nonvolatile binary resistance-switches (in a high resistance state (HRS) or low resistance state (LRS)) in response to a [...] Read more.
An artificial neural network was utilized in the behavior inference of a random crossbar array (10 × 9 or 28 × 27 in size) of nonvolatile binary resistance-switches (in a high resistance state (HRS) or low resistance state (LRS)) in response to a randomly applied voltage array. The employed artificial neural network was a multilayer perceptron (MLP) with leaky rectified linear units. This MLP was trained with 500,000 or 1,000,000 examples. For each example, an input vector consisted of the distribution of resistance states (HRS or LRS) over a crossbar array plus an applied voltage array. That is, for a M × N array where voltages are applied to its M rows, the input vector was M × (N + 1) long. The calculated (correct) current array for each random crossbar array was used as data labels for supervised learning. This attempt was successful such that the correlation coefficient between inferred and correct currents reached 0.9995 for the larger crossbar array. This result highlights MLP that leverages its versatility to capture the quantitative linkage between input and output across the highly nonlinear crossbar array. Full article
(This article belongs to the Special Issue Nanoscale Switches)
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14 pages, 6777 KiB  
Article
Asymmetrical Training Scheme of Binary-Memristor-Crossbar-Based Neural Networks for Energy-Efficient Edge-Computing Nanoscale Systems
by Khoa Van Pham, Son Bao Tran, Tien Van Nguyen and Kyeong-Sik Min
Micromachines 2019, 10(2), 141; https://doi.org/10.3390/mi10020141 - 20 Feb 2019
Cited by 25 | Viewed by 4433
Abstract
For realizing neural networks with binary memristor crossbars, memristors should be programmed by high-resistance state (HRS) and low-resistance state (LRS), according to the training algorithms like backpropagation. Unfortunately, it takes a very long time and consumes a large amount of power in training [...] Read more.
For realizing neural networks with binary memristor crossbars, memristors should be programmed by high-resistance state (HRS) and low-resistance state (LRS), according to the training algorithms like backpropagation. Unfortunately, it takes a very long time and consumes a large amount of power in training the memristor crossbar, because the program-verify scheme of memristor-programming is based on the incremental programming pulses, where many programming and verifying pulses are repeated until the target conductance. Thus, this reduces the programming time and power is very essential for energy-efficient and fast training of memristor networks. In this paper, we compared four different programming schemes, which are F-F, C-F, F-C, and C-C, respectively. C-C means both HRS and LRS are coarse-programmed. C-F has the coarse-programmed HRS and fine LRS, respectively. F-C is vice versa of C-F. In F-F, both HRS and LRS are fine-programmed. Comparing the error-energy products among the four schemes, C-F shows the minimum error with the minimum energy consumption. The asymmetrical coarse HRS and fine LRS can reduce the time and energy during the crossbar training significantly, because only LRS is fine-programmed. Moreover, the asymmetrical C-F can maintain the network’s error as small as F-F, which is due to the coarse-programmed HRS that slightly degrades the error. Full article
(This article belongs to the Special Issue Nanoscale Switches)
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12 pages, 2301 KiB  
Article
A Novel Defect Tolerance Scheme for Nanocrossbar Architectures with Enhanced Efficiency
by Devisree Sasikumar and Anand Kumar
Micromachines 2019, 10(1), 14; https://doi.org/10.3390/mi10010014 - 27 Dec 2018
Cited by 1 | Viewed by 2626
Abstract
The semiconductor industry is now facing challenges to keep pace with Moore’s law and this leads to the requirement of new materials and newer technological devices. Molecular switch-based nanodevices are one of the promising areas because of their ultimate size and miniaturisation potential. [...] Read more.
The semiconductor industry is now facing challenges to keep pace with Moore’s law and this leads to the requirement of new materials and newer technological devices. Molecular switch-based nanodevices are one of the promising areas because of their ultimate size and miniaturisation potential. These nanodevices are built through a self-assembled bottom-up manufacturing method in which the possibility of external intervention is negligible. This leads to a considerable yield loss due to defective device production and the traditional test-and-throw faulty device approach will not hold well. Design of fault-tolerant devices are the only possible solution. A widely studied nanodevice is nanocrossbar architectures and their fault tolerance can be designed by exploiting the programmable logic array’s fault tolerance schemes. A defect-unaware fault tolerance scheme is developed in this work based on the bipartite graph analogy of crossbar architectures. The newly-designed algorithm can eliminate more than one node in each iteration and, hence, a defect-free subcrossbar can be obtained much faster compared to the existing algorithms. A comparison with the existing defect-unaware fault-tolerant methods with this newly-developed algorithm shows a better yield in most of the cases. Full article
(This article belongs to the Special Issue Nanoscale Switches)
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