Voltage-Controlled Spin-Orbit-Torque-Based Nonvolatile Flip-Flop Designs for Ultra-Low-Power Applications

Abstract

Flip-flop (FF) serves as a fundamental unit in various sequential logic circuits and complex digital electronic systems for generating, transforming, and temporarily storing digital signals. Nonvolatility plays a crucial role in FFs by ensuring instant data recovery after unexpected data loss. Nonvolatile flip-flop can quickly recover in a self-powered environment, making it suitable for application environments such as the Internet of Things (IOT). Unfortunately, most existing nonvolatile FFs (NVFFs) suffer from extended delays and high energy consumption during data backup and restore operations. In this paper, we propose two innovative voltage-controlled nonvolatile FFs (VC-FFs), namely VC-DFF (voltage-controlled D-FF) and VC-SRFF (voltage-controlled SR-FF), which address these challenges using voltage-controlled spin-orbit torque (VC-SOT) devices. The proposed designs are evaluated using a 40 nm CMOS process. Simulation results demonstrate that the proposed designs achieve significant improvements in write (recovery) energy consumption, with over 7.2× (1.54×) and 18.7× (2×) enhancements compared to their STT- and SOT-based counterparts, respectively.

1. Introduction

With the continuous development of the Internet of Things, various IoT devices have been integrated into our daily lives. Due to the complexity of the working environment and the requirement for portability of portable devices, these IoT devices do not meet the conditions to be equipped with high-capacity batteries or wired power supplies [1]. The energy supply in the Internet of Things environment is mostly obtained through changes in external environments such as solar energy, wind energy, and vibration. This constantly changing and unpredictable external environmental change may lead to an unstable energy supply [2], leading to frequent power outages and system restarts. Flip-flop (FF) is a basic unit in sequential logic circuits that can be used to store and transfer temporary digital signals. The traditional FFs are composed of CMOS devices, which can realize basic operations such as resetting, setting, triggering, and maintenance. SR flip-flop (SRFF) and D flip-flop (DFF) are two typical representatives of basic FFs, which can be used as the basis for designing other types of FFs. As shown in Figure 1, for CP = “0”, the output Q and QB of the SRFF (or DFF) only depend on the initial states. For CP = “1”, the state tradition diagrams of the SRFF and DFF are shown in Figure 1b,d, respectively. FF is a typical volatile device, which means that power outages can cause data loss.

The inability to predict the time and location of the next outage from an unstable power supply makes data protection a key challenge. If the FF is nonvolatile and is able to maintain the state after powering off, the whole system can support transient data recovery. Recently, nonvolatile FF (NVFF) has attracted great interest in power-gating applications and a number of NVFF designs have been proposed by integrating nonvolatile memory (NVM) devices [1,2,3,4,5,6,7]. In the NVFFs, data are first stored in the NVMs when the system is in the standby state, and they are then restored back into the regular FFs when the system is powered on [8,9,10,11,12,13,14,15,16]. In this case, run-time data can be maintained even if a power interruption happens.

Nevertheless, most of the current nonvolatile FFs (NVFFs) suffer from long delays and high energy in the data backup and restore operations. Many efforts have been made and many NVFF designs have been proposed to minimize the latency needed for data transportation. Biglari et al. presented two bipolar ReRAM-based NVFFs [17]. In this design, both the endurance and the energy efficiency are improved. In addition, an area-efficient NVFF based on a spin-torque transfer magnetic tunnel junction (STT-MTJ) was proposed [18]. It has an improvement of nearly a factor of 4–23 in terms of area overhead compared to previous NVFF architectures. To reduce the energy, Deng et al. proposed four NVFF designs based on either DFF or SRFF architecture and perpendicular MTJs (pMTJs) [19]. These designs can achieve a fast reading speed (<200 ps), low read power (<10 fJ), and high area efficiency. However, when the power supply is unstable or the system is frequently powered off, the above designs cannot work normally. Some NVFFs [10,11,15,20] involve a power supply state detection circuit, so that data can be backed up into NVMs in time when the system is powered off. Nevertheless, these additional circuits not only increase the complexity but also degrade the performance. To achieve shorter delay and better area efficiency, Chang et al. proposed a memristor-based NV-DFF [21]. In ref. [21], the functions are accomplished by reading and writing RRAM devices. However, the repeated reading and writing operations of RRAM devices bring high delay and high power consumption. On the other hand, NVFFs using magnetic tunnel junctions (MTJs) are the most popular candidates. MTJ has the advantages of nonvolatility, low power consumption and high speed. It can be programmed using different methods, such as field-induced magnetization (FIM) reversal, spin transfer torque (STT), and spin-orbit torque (SOT). FIM requires an external magnetic field to program the MTJ, which increases energy consumption and hinders its scalability. STT needs a large drive current, which brings high write power consumption, and the same read–write operation path will also bring read–write crosstalk problems. Recently, a new MTJ device with an in-plane exchange bias (EB) called voltage-controlled spin-orbit torque (VC-SOT) has received extensive attention from academia and industry [22]. With the aid of an in-plane exchange bias, the VC-SOT MTJ can be switched without an additional field. By controlling the bias voltage applied to the MTJ and the bidirectional SOT current through the anti-ferromagnetic (AFM) layer, the MTJ can be switched at a fast speed. In addition, the read–write current of the VC-SOT MTJ device is lower than that of STT-MTJ and SOT-MTJ devices. The lower current makes the VC-SOT MTJ device consume less energy during the read and write operations.

In this paper, based on the VC-SOT-MTJ device, we propose two novel NVFFs, making the following main contributions:

(1)

We proposed a symmetric complementary scheme, employing two back-to-back connected VC-SOT-MTJ devices to enable fast data configuration and a high reading threshold;

(2)

We proposed a simple working method for the NVFF to enable traditional FF functions and nonvolatility;

(3)

We proposed two high-speed, energy-efficient VC-FF designs with simpler circuit structures and lower area overhead.

The remainder of this paper is organized as follows: Section 2 introduces the basic structure and operation of the VC-SOT MTJ device; Section 3 illustrates the operation mechanism of the proposed VC-DFF and VC-SRFF; Section 4 presents the experimental results; finally, Section 5 concludes the paper.

2. Basic Structure of the VC-SOT MTJ Device

Spintronic devices achieve the injection, transport, and detection of spin current by regulating the spin properties of electrons, thereby achieving the processing, transmission, and representation of electronic signals. Magnetic tunnel junction is a way to control electron spin in spintronics. By adjusting the magnetization direction of the ferromagnetic layer in the magnetic tunnel junction, it exhibits different macroscopic electrical characteristics, such as resistance, performed to achieve data storage or calculation. The methods of regulating magnetic tunnel junctions generally include applying magnetic fields, currents, and voltages.

A typical VC-SOT MTJ structure (Figure 2a) contains an anti-ferromagnetic (AFM) layer (e.g., IrMn) with an MTJ positioned on top of it. The MTJ consists of three layers: the ferromagnetic (FM, e.g., CoFeB) pinned layer, the oxide layer (e.g., MgO), and the FM-free layer. The magnetization direction of the pinned layer remains fixed, while the free layer’s magnetization direction can be freely altered. When the magnetization direction of the free layer is anti-parallel (AP) to the pinned layer, the MTJ is in a high resistance state. Conversely, when the magnetization direction of the free layer is parallel (P) to the pinned layer, the MTJ is in a low resistance state. These two resistive states of the MTJ can represent data “1” and “0” (AP for “1”, P for “0”). A recent discovery involves a novel magnetic field-free switching mechanism [19], which utilizes an IrMn/CoFeB/MgO structure and achieves field-free SOT switching aided by an in-plane EB. As shown in Figure 2a, the new mechanism also incorporates the voltage control of the magnetic anisotropy (VCMA) effect, significantly reducing the SOT switching current by applying a bias gate voltage (V_bia). The magnetization of the free layer in the MTJ device can be pulled towards the in-plane direction by both the SOT and voltage torques. In addition, in-plane magnetic symmetry is disrupted by the exchange bias between the AFM/FM (IrMn/CoFeB) layers of the MTJ. In sub-nanoseconds, the deterministic and complete reversal of the magnetization in the free layer of the MTJ device can be achieved.

Figure 2b shows a typical VC-SOT MTJ bit-cell structure. It consists of a VC-SOT MTJ and two NMOS transistors. During the write operation, for V₀ = “1”, a write voltage is applied between VT₁ and VT₂ to generate a write current (Iwrite). The magnetization direction of the free layer of MTJ is then switched based on the direction of Iwrite. Simultaneously, V₁ = “1”, and a bias voltage (V_bia) is connected to the MTJ, reducing the energy barrier required for the magnetization direction switch. The read operation follows a different path. Specifically, during the read operation, the read current (Iread) flows through the MTJ, with the MTJ state determining the amplitude of Iread.

3. Proposed VC-FFs

Traditional NVFFs generally include a power state detection circuit, control circuit, volatile FF circuit, nonvolatile memory and peripheral read–write circuits. When the NVFF encounters an unexpected power failure, the power supply state detection circuit can detect the power supply state and transmit the signal to the control circuit. The control circuit controls the read–write circuits of the NVFF for data backup operation. Compared with the traditional NVFFs, the VC-FFs proposed in this paper consist of basic CMOS transistors and VC-SOT-MTJ devices. The proposed VC-FFs can realize the basic functions of traditional FFs with nonvolatility. The circuit structure and working principle are much simpler compared to previous NVFF designs. This section presents the schematic and principle of the VC-DFF and VC-SRFF.

3.1. VC-DFF Circuit Architecture and Operations

The architecture of the VC-DFF is illustrated in Figure 3. It mainly consists of two VC-SOT MTJs (M_data and M_ref), four control transistors (N₂~N₅), five transmission transistors (N₁ and N₆~N₉), three inverters (INV₁~INV₃) and a pre-charge sensing amplifier (PCSA) [20,23]. In this architecture, D represents the input data. CLK and CLKB are two complementary clock signals. Q and QB represent two complementary output signals. M_data and M_ref are data cell and reference cells, respectively, used to store one single bit. Cr represents the read control signal, which is employed to read the data stored in the MTJ device. It is defined by the following formula:

$$\mathrm{C}\mathrm{r}=\left\{\begin{array}{c}0, 0\ll t<\frac{\mathrm{T}}{4}\\ 1, \frac{\mathrm{T}}{4}\ll t<\frac{\mathrm{T}}{2}\\ \mathrm{CLKB}, t\gg \frac{\mathrm{T}}{2}\end{array}\right.\mathrm{a}=1,$$

(1)

where T represents a clock cycle. The control signal Cr is always consistent with CLKB, except for the first half of the clock cycle. The VC-DFF uses a symmetric complementary scheme, where two MTJs are used to store one bit. As shown in Figure 3, both the T3 terminals of M_data and M_ref are shorted to ensure the opposite direction of the writing current. It is noted that M_data and M_ref are in complementary states. This complementary approach for data storage improves the read margin of the PCSA. The increase in the read margin greatly improves the speed and reliability. The working status of the VC-DFF can be divided into normal mode, standby/power off mode, and recovery mode, based on the power supply status of the circuit.

3.1.1. Normal Mode

In this state, the traditional NVFF [14,15,16,17,18] separates the MTJs from the FF circuits via the transmitting transistors. As a result, the NVFFs work like traditional FFs. However, if the data are not backed up in time, there is still a risk of data loss, especially in the case of intermittent powering off. Traditional NVFFs need to perform the data backup operation before switching off the power supply in case of unexpected power failure. Unlike the traditional NVFFs, the proposed VC-DFF does not easily lose the data of the DFF. The input data can be saved in normal operation mode, so the VC-DFF does not require an additional backup operation in case of system power failure. In this state, the signal Cr is determined by the signal CLKB. As shown in Figure 3a, when CLK = “1”, N₁ turns on while N₆~N₉ turn off. The state of Q is consistent with that of the input signal D. The state diagram of the VC-DFF is the same as shown in Figure 1d. The voltages of the two write control signals V_sot and V_bia are set to V_dd. N₄ and N₅ are turned on, and the bias voltages of MTJs (M_data and M_ref) rise to V_dd. Increasing the bias voltage reduces the energy barrier of the VC-MTJ devices. It is particularly noteworthy that the two VC-SOT-MTJ devices are connected back to back. The structure can ensure that the magnetization direction of two devices is always reversed to a complementary state when the write current passes through the two devices. Specifically, for D = “0”, a SOT write current flows from M_ref to M_data. The write operation is completed by switching the magnetization of M_ref and M_data to the AP (“1”) and P (“0”) states, respectively. It should be noted that the voltage of Cr is always locked at GND when CLK = “1”, causing the node out₊ (out₋) in the PCSA to rise to ${\mathrm{V}}_{\mathrm{d}\mathrm{d}}$ before the read operation. As shown in Figure 2b, when CLK = “0”, N₆~N₉ turn on while N₁~N₅ turn off. In this case, Q follows the state of out₊. The data voltage signal (V_T1+) and the reference voltage signal (V_T1−) are involved in the sensing operation of the PCSA. Finally, the PCSA generates the readout output. As mentioned above, data are always stored in a complementary state in the MTJ devices. Therefore, this symmetrical structure can maximize the read margin and the stability of the PCSA.

3.1.2. Standby/Power off Mode

When the system is unexpectedly powered down, the traditional NVFFs require an additional power supply state detection circuit to determine when the data are backed up or restored. The detection circuit makes the circuit more complicated, and the detection and backup/reduction operations also increase the energy consumption and latency. Note that the VC-DFF completes the storage of data in the VC-SOT MTJs during normal working mode. The controller can power off unused modules to reduce the static power consumption. Even if a power interruption occurs, there is no need for additional state detection and data backup operations to handle the power interruption.

3.1.3. Restore Mode

After the power supply is restored, only the read operation of the MTJs is required. According to Equation (1), with an appropriate excitation signal Cr, data stored in MTJs can be read out by the PCSA for data recovery. As can be seen, the input data D are stored in the nonvolatile MTJ during the normal mode. After the power supply is restored, only the read operation of the MTJs is required. The VC-DFF can realize ultra-low energy consumption during the recovery operation, without any stationary currents and dynamic charging/discharging currents. Due to the absence of backup operations, the VC-DFF avoids the power, delay and area overhead for data backup. Compared to existing designs, our work achieves higher speed and energy efficiency.

3.2. VC-SRFF Circuit Architecture and Operations

Figure 4 illustrates the VC-SRFF structure, which shares a similar working principle to the VC-DFF proposed in Section 3.1. To explain the VC-SRFF’s working principle, we use the example of setting R = “0”, S = “1”. As shown in Figure 4a, when CLK = “1”, N₁ is turned on while N₆~N₉ are turned off. Consequently, an SOT writes current flows from M_ref to M_data, writing the data “1” and “0” into M_ref and M_data, respectively. Simultaneously, the PCSA performs the pre-charging operation. When CLK = “0”, N₆~N₉ are turned on while N₁~N₅ are turned off. In this scenario, Q follows the state of out₊. The sensing operation of the PCSA involves the data voltage signal (V_T1+) and the reference voltage signal (V_T1−). Finally, the PCSA generates the readout output. The standby/power off mode and restore mode are not different from VC-DFF.

4. Simulations and Discussions

Based on the circuits shown in Figure 3 and Figure 4, the proposed VC-DFF and VC-SRFF are designed and evaluated using a 40 nm CMOS design kit. The parameters of the VC-SOT MTJ and variables are summarized in

Table 1. Parameters and variables of the VC-SOT-MTJ model.

Parameter	Description	Default Value
Ki	Interfacial anisotropy density	1.005 × 10−6 KJ/m2
MS	Saturation magnetization	1.2 × 106 A/m
§	Voltage control coefficient	75 fJ/V·m
D	Diameter of the free layer	80 nm
tOX	Oxide layer height	1.5–2.5 nm
tFL	Free layer thickness	1.1 nm
l,w,d	Heavy metal dimension	100 nm, 100 nm, 3 nm
α	Magnetic damping constant	0.02
θ	Spin Hall angle	0.3
rho	Heavy metal resistivity	200 μΩ · cm
Hex	Exchange bias field	−7956 A/m
T	Temperature	300 K
Vdd	Voltage	1.2 V
Υ	Gyromagnetic ratio	2.21276 × 105 m/(A·s)
μ0	Permeability in free space	1.2566 × 106 H/m
kB	Boltzmann constant	1.38 × 10−23 J/K
e	Elementary charge	1.6 × 10−19 C

.

Figure 5 presents the transient simulation waveforms of the VC-DFF. As shown in Figure 5a,b, the VC-DFF begins with a normal mode (writing process and reading process), which is consistent with the description in Section 3.1.1. During the writing process, since Cr is always set to “0” and the PCSA circuit remains in the pre-charging stage, resulting in OUT₊ = OUT₋ = “1”. The output value Q changes accordingly with D. When performing a write operation, V_bia and V_sot need to apply a positive pulse voltage (pulse width of 1 ns and 1.2 ns, respectively). As shown in Figure 5a, when D = ‘0’ and V_sot and V_bia apply a positive pulse voltage, the magnetization direction of the MTJ device in M_data transitions from the AP to P state, completing nonvolatile storage of data “0”. When D changes from “0” to “1”, the magnetization direction of the MTJ device in M_data changes from P to AP state, completing the nonvolatile storage of data “1”. The main difference between Figure 5a and b lies in the difference in the initial data stored in M_data. From Figure 5b, it can be seen that when the written data are consistent with the original data, the magnetization direction of MTJ does not change. The simulation results show that the write delay of the MTJ device is 4 ns. The states of M_data and M_ref are always complementary.

During the read process, CLK is set to “0” and Cr is set to “1”. The output Q during the reading process depends on the latest written data (“1”) from the previous writing process. During the reading process, when D changes, the output result remains unchanged. The VC-DFF does not require any additional operations when the system cuts off the module power to save energy or encounters an unexpected power off, as shown in Figure 5a.

The recovery mode essentially performs a reading operation of the resistance state stored in M_data by the PCSA circuit. As shown in Figure 5a, when the state of M_data is AP, the output value Q during the recovery process is “1”. As shown in Figure 5b, when the state of M_data is P, the output value Q during the recovery process is “0”, which is consistent with the expected result. The simulation results in Figure 5 demonstrate that the VC-DFF can successfully operate in the modes, achieving data recovery and normal reading and writing processes.

Figure 6 presents the transient simulation waveforms of the VC-SRFF. In the normal mode, the VC-SRFF functions similarly to the VC-DFF. When S and R are set to different logic levels, and the output terminals Q and QB have two complementary stable states. As shown in Figure 6, when S = “0” and R = “1”, a SOT write current flows from M_ref to M_data. The write operation is achieved by switching the magnetization of M_ref and M_data to AP and P, respectively. When S = “1” and R = “0”, a SOT write current flows from M_ref to M_data. The magnetizations of M_ref and M_data are switched to P and AP states, respectively. During the read processes, the output result Q is not affected by changes in S and R. The value of Q is the data stored in M_data after the last write operation. The operation in the data recovery phase is the same as the operation process in VC-DFF, which essentially involves reading the data stored in MTJs. The simulation results in Figure 6 show that VC-SRFF works successfully in all modes.

Table 2. Performance comparison.

	STT-Based NVDFF [12]	STT-Based NVDFF [24]	SOT-Based NVDFF [19]	SOT-Based NVDFF [8]	Proposed VC-DFF/VC-SRFF
Technological Node (nm)	40	20	40	45	40
Number of Devices	21T + 2MTJ	28T + 2MTJ	21T + 2MTJ	16T + 1MTJ	20T + 2MTJ/24T + 2MTJ
Twrite (ns)	35.7	4.1	1.6	4	1.7
Write Power Consumption (fJ/bit)	4780	54.5	131.4	218	6.64
TRecovery (ns)	>0.1	0.24	0.2	0.3	0.16
Recovery Power Consumption (fJ/bit)	5	14.5	6.7	6	3.24

compares the performance of our work with the state-of-the-art NVFFs [8,12,19,24]. As can be seen, ref. [8] has a certain area advantage, but it has a large read–write power consumption. However, the total number of devices in this paper represents the number of all devices involved in the work, while the number of devices in the STT-based NVFF [12,24] and the SOT-based NVFF [8,19] does not include the number of devices in the peripheral state detection circuit. Compared to the STT-based NVFF [12,24], our work can achieve up to a 20× (1.4×) reduction in write latency. Moreover, in terms of write power consumption, our work shows up to a 718× (7.2×) and 18.7× (31×) improvement compared to the STT-based NVFF [12,24] and the SOT-based NVFF [8,19], respectively. Additionally, the recovery power consumption of the STT-based NVFF [8,12] is 1.54 (3.47) times that of our work, while the SOT-based NVFF is about twice that of our work. The main reason for the significant reduction in write and recovery power consumption is the complexity of the circuit architecture. Specifically, the STT-based NVFF not only requires an additional system power state detection circuit for backup and restore operations but also additional write circuits and complex control logic gates for data-writing operations. In comparison, the SOT-based NVFF only requires a system power state detection circuit, resulting in a simpler circuit design. The VC-FFs we propose do not require additional peripheral circuits. Therefore, among these three designs, our work exhibits the simplest structure and best performance. Although VC-FFs provide very low read and write power consumption for nonvolatile devices in normal operating mode, additional read and write operations inevitably result in unnecessary power consumption. In order to reduce the power consumption, we will optimize the read and write operation mode of the FF in future work.

5. Conclusions

In this paper, we propose two novel VC-FFs (VC-DFF and VC-SRFF) based on a VC-SOT MTJ device. The VC-FFs consist of a limited number of transmission gates, CMOS inverters and two VC-SOT MTJs. Without additional write peripheral circuits and system power state detection circuits, the proposed VC-FFs show a significant reduction in both area overhead and operation complexity compared to the state-of-the-art NVFFs. In our work, a symmetrical structure is used to maximize the margin and the stability of the PCSA. The VC-FFs are designed and evaluated with a 40 nm CMOS design kit. The simulation results show that our proposed VC-FFs reduce the write power consumption by more than 7.2× and 18.7× compared to the STT-based NVFF and SOT-based NVFF, respectively. Additionally, the recovery power consumption of our work is 1.54 times less than that of the STT-based NVFF and twice as low as than that of the SOT-based NVFF.