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Advanced Integrated Circuits and Devices
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Advanced Integrated Circuits and Devices

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (22 September 2023) | Viewed by 7196

Special Issue Editors

Dr. Wang Kang

E-Mail Website
Guest Editor
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
Interests: spintronics; in-memory computing; IC design
Special Issues, Collections and Topics in MDPI journals
Dr. Biao Pan

E-Mail Website
Guest Editor
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
Interests: digital circuits design; in-memory computing; brain-inspired computing
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

With the rapid development of big data and artificial intelligence, higher requirements have been put forward for the speed, density, power consumption and cost of integrated circuits. Particularly, increasing computation leads to bottlenecks in von Neumann-based computing architecture, which has motivated tremendous efforts to develop novel memory devices, smart circuits and advanced computing architectures. This Special Issue intends to present new ideas and experimental results in the field of advanced integrated circuits and devices from theory, design, and experiments to practical uses. Areas relevant to this field include but are not limited to, novel devices, advanced integrated circuits, computing architectures, and applications.

This Special Issue will publish unpublished, high-quality original research papers in the overlapping fields of:

  • Novel memory and computing devices (RRAM, MRAM, PCM, FeFET, etc.).
  • Advanced circuits and architectures, such as in-memory computing, quantum computing, brain-inspired computing, stochastic computing, optical computing, etc.
  • Systems and demonstrations with the above advanced circuits and devices.
  • Device/circuit/architecture-related reliability, power, performance, applications, etc.

Dr. Wang Kang
Dr. Biao Pan
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • emerging devices
  • RRAM
  • MRAM
  • PCM
  • FeFET
  • novel computing architectures
  • in-memory computing
  • quantum computing
  • brain-inspired computing
  • stochastic computing
  • optical computing

Published Papers (5 papers)

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Research

10 pages, 2024 KiB  
Article
Voltage-Controlled Spin-Orbit-Torque-Based Nonvolatile Flip-Flop Designs for Ultra-Low-Power Applications
by Xiao Liu, Erya Deng, Lichuan Luo, Linjun Jiang, Youguang Zhang, Dijun Liu, Biao Pan and Wang Kang
Appl. Sci. 2023, 13(20), 11316; https://doi.org/10.3390/app132011316 - 15 Oct 2023
Viewed by 924
Abstract
Flip-flop (FF) serves as a fundamental unit in various sequential logic circuits and complex digital electronic systems for generating, transforming, and temporarily storing digital signals. Nonvolatility plays a crucial role in FFs by ensuring instant data recovery after unexpected data loss. Nonvolatile flip-flop [...] Read more.
Flip-flop (FF) serves as a fundamental unit in various sequential logic circuits and complex digital electronic systems for generating, transforming, and temporarily storing digital signals. Nonvolatility plays a crucial role in FFs by ensuring instant data recovery after unexpected data loss. Nonvolatile flip-flop can quickly recover in a self-powered environment, making it suitable for application environments such as the Internet of Things (IOT). Unfortunately, most existing nonvolatile FFs (NVFFs) suffer from extended delays and high energy consumption during data backup and restore operations. In this paper, we propose two innovative voltage-controlled nonvolatile FFs (VC-FFs), namely VC-DFF (voltage-controlled D-FF) and VC-SRFF (voltage-controlled SR-FF), which address these challenges using voltage-controlled spin-orbit torque (VC-SOT) devices. The proposed designs are evaluated using a 40 nm CMOS process. Simulation results demonstrate that the proposed designs achieve significant improvements in write (recovery) energy consumption, with over 7.2× (1.54×) and 18.7× (2×) enhancements compared to their STT- and SOT-based counterparts, respectively. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits and Devices)
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23 pages, 23352 KiB  
Article
Multi-Mode Lithium-Ion Battery Balancing Circuit Based on Forward Converter with Resonant Reset
by Yanliang Zong, Kun Li, Qing Wang and Jiaheng Meng
Appl. Sci. 2023, 13(18), 10430; https://doi.org/10.3390/app131810430 - 18 Sep 2023
Cited by 1 | Viewed by 928
Abstract
A multi-mode active balancing circuit based on a forward converter with resonant reset is proposed to deal with unbalanced states of lithium-ion battery packs. The balancing circuit utilizes the forward converter, enabling high-power balancing. SPST relays are selected to constitute the switching matrix, [...] Read more.
A multi-mode active balancing circuit based on a forward converter with resonant reset is proposed to deal with unbalanced states of lithium-ion battery packs. The balancing circuit utilizes the forward converter, enabling high-power balancing. SPST relays are selected to constitute the switching matrix, and the proposed balancing circuit completes the connection of serial battery clusters to the main circuit by controlling the SPST relays, realizing the Multi-Cell-to-Multi-Cell (MC2MC) balancing method. An “adaptive selection mode based on the state of high energy battery” balancing strategy is proposed. The proposed balancing strategy allows the proposed balancing circuit to have multiple balancing modes, flexible balancing paths, and switching between different balancing processes in real time, significantly improving the balancing speed. The inherent LC resonant reset structure of the forward converter is employed to achieve MOSFET zero-voltage switching (ZVS). To optimize the balancing performance, the circuit model is built and the balancing parameters in the circuit are analyzed. An experiment with an eight-cell lithium-ion battery pack was performed to verify the balancing effect of the proposed circuit, and comparison with a typical balancing circuit was carried out. Experimental results show that the proposed balancing circuit has a faster balancing speed. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits and Devices)
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10 pages, 3251 KiB  
Article
A 12.4–32 GHz CMOS Down-Conversion Mixer for 28 GHz 5G New Radio (NR)
by Yo-Sheng Lin and Kai-Siang Lan
Appl. Sci. 2023, 13(4), 2305; https://doi.org/10.3390/app13042305 - 10 Feb 2023
Viewed by 1192
Abstract
We report a low voltage (VDD) and power (PDC) 12.4–32 GHz CMOS down-conversion mixer with high conversion gain (CG) for 28 GHz 5G communications. A quarter-wavelength (λ/4) transmission line (TL) and a coupling capacitor (Cc), named the [...] Read more.
We report a low voltage (VDD) and power (PDC) 12.4–32 GHz CMOS down-conversion mixer with high conversion gain (CG) for 28 GHz 5G communications. A quarter-wavelength (λ/4) transmission line (TL) and a coupling capacitor (Cc), named the λ/4-TL-C-based coupler, is proposed. This is the way to attain low-VDD, independent RF transconductance (gm)-stage bias, harmonic suppression, and near perfect coupling from the RF gm stage to the LO switch transistors. The body-self-forward-bias (BSFB) technique, i.e., connection of the gm-stage transistors’ body to drain via a large body resistance, is used for threshold voltage (Vth) and VDD reduction and substrate leakage suppression. CG and noise figure (NF) enhancement at the same or even a lower PDC is achieved because lower VDD and higher gm (due to larger bias current) are used. To facilitate the RF measurement, a compact Wilkinson-power-divider-based balun with small-phase deviation and amplitude imbalance is included at RF and LO inputs. The mixer consumes 6.5 mW and achieves a CG of 14.4 ± 1.5 dB for 12.4–32 GHz (i.e., 3 dB bandwidth (f3dB) of 19.6 GHz), a lowest noise figure (NFmin) of 7 dB, and figure-of-merit (FOM) of 0.023, which is one of the best results ever reported for millimeter-wave (mm-wave) down-conversion mixers with an f3dB larger than 10 GHz and PDC lower than 10 mW. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits and Devices)
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17 pages, 6292 KiB  
Article
An 8kb RRAM-Based Nonvolatile SRAM with Pre-Decoding and Fast Storage/Restoration Time
by Jiayu Yin, Wenli Liao, Yuyan Zhang, Jianhua Jiang and Chengying Chen
Appl. Sci. 2023, 13(1), 531; https://doi.org/10.3390/app13010531 - 30 Dec 2022
Cited by 4 | Viewed by 1652
Abstract
Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot [...] Read more.
Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits and Devices)
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10 pages, 1784 KiB  
Article
Magnetic Skyrmion-Based Spiking Neural Network for Pattern Recognition
by Shuang Liu, Guangyao Wang, Tianshuo Bai, Kefan Mo, Jiaqi Chen, Wanru Mao, Wenjia Wang, Zihan Yuan and Biao Pan
Appl. Sci. 2022, 12(19), 9698; https://doi.org/10.3390/app12199698 - 27 Sep 2022
Cited by 2 | Viewed by 1707
Abstract
Spiking neural network (SNN) has emerged as one of the most powerful brain-inspired computing paradigms in complex pattern recognition tasks that can be enabled by neuromorphic hardware. However, owing to the fundamental architecture mismatch between biological and Boolean logic, CMOS implementation of SNN [...] Read more.
Spiking neural network (SNN) has emerged as one of the most powerful brain-inspired computing paradigms in complex pattern recognition tasks that can be enabled by neuromorphic hardware. However, owing to the fundamental architecture mismatch between biological and Boolean logic, CMOS implementation of SNN is energy inefficient. A low-power approach with novel “neuro-mimetic” devices offering a direct mapping to synaptic and neuronal functionalities is still an open area. In this paper, SNN constructed with novel magnetic skyrmion-based leaky-integrate-fire (LIF) spiking neuron and the skyrmionic synapse crossbar is proposed. We perform a systematic device-circuit-architecture co-design for pattern recognition to evaluate the feasibility of our proposal. The simulation results demonstrated that our device has superior lower switching voltage and high energy efficiency, two times lower programming energy efficiency in comparison with CMOS devices. This work paves a novel pathway for low-power hardware design using full-skyrmion SNN architecture, as well as promising avenues for implementing neuromorphic computing schemes. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits and Devices)
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