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Micromachines
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High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition
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High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: closed (20 June 2024) | Viewed by 8897

Special Issue Editors

Dr. Yiqiang Chen

E-Mail Website
Guest Editor
Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, The No.5 Electronics Research Institute of the Ministry of Industry and Information Technology, Guangzhou 510610, China
Interests: failure mechanism and model of key devices; prognostics and health management (PHM) of power conversion system (PCS); PHM of system on chip (SoC)
Special Issues, Collections and Topics in MDPI journals
Dr. Yi Liu

E-Mail Website
Guest Editor
School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: integrated circuits design; simulation and evaluation method of radiation effects in aerospace integrated circuits
Special Issues, Collections and Topics in MDPI journals
Dr. Changqing Xu

E-Mail Website
Guest Editor
Guangzhou institute of technology, School of Microelectronics, Xidian University, Xi’an 710071, China
Interests: VLSI design and optimization; brain-inspired computing; EDA technology
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In this Special Issue on “High-Reliability Semiconductor Devices and Integrated Circuits”, we will focus on simulation, modeling, design, and optimization for high-reliability devices and integrated circuits for automobiles, avionics, and aerospace. High-reliability devices and integrated circuits are intensely studied because they are widely used in traditional aerospace electronic systems, avionics, automobiles, etc. In recent years, in addition to the development of traditional highly reliable devices and circuits, new technologies such as intelligent analysis, optimization, and manufacturing based on artificial intelligence and other novel technologies have brought vitality to the field of high-reliability devices and circuits.

The objective of this Special Issue is to collect research works focused on mathematical models, high-efficiency/-precision numerical solution methods, and intelligent design and optimization methods for high-reliability materials and devices and integrated circuits. We welcome novel works reporting on high-reliability devices and circuits and their applications to discuss the most recent breakthroughs and the potential impacts in related research fields. The specific topics of interest include, but are not limited to, the following:

  • Novel design methods for high-reliability devices and integrated circuits;
  • Novel optimization technologies for high-reliability devices and integrated circuits;
  • Advanced device structures or materials for high-reliability design;
  • Reliability analyses of special environments, such as those with a strong magnetic field, radiation environment, etc.;
  • Applications of novel technology, such as AI, in high-reliability design and analysis;
  • Novel simulation technologies for functional safety.

Dr. Yiqiang Chen
Dr. Yi Liu
Dr. Changqing Xu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • high reliability
  • semiconductor devices
  • integrated circuits
  • strong magnetic field
  • radiation environment
  • intelligent design

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Related Special Issue

Published Papers (10 papers)

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Research

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16 pages, 37562 KiB  
Article
Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling
by Wenchao Tian, Haojie Dang, Dexin Li, Yunhao Cong and Yuanming Chen
Micromachines 2024, 15(8), 986; https://doi.org/10.3390/mi15080986 - 30 Jul 2024
Viewed by 514
Abstract
As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts [...] Read more.
As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts a thermo-mechanical analysis of TSV structures within multi-layered complex interposers, and analyzes the thermal stress behavior and reliability under variable temperature conditions (−55 °C to 85 °C), taking into account the typical electroplating defects within the copper pillars in TSVs. Initially, an overall model is established to determine the critical TSV locations. Sub-model analysis is then employed to investigate the stress and deformation of the most critical TSV, enabling the calculation of the temperature cycle life accordingly. Results indicate that the most critical TSV resides centrally within the model, exhibiting the highest equivalent stress. During the temperature cycling process, the maximum deformation experiences approximately periodic variations, while the maximum equivalent stress undergoes continuous accumulation and gradually diminishes. Its peak occurs at the contact interface corner between the TSV and Redistribution Layer (RDL). The estimated life of the critical point is 3.1708 × 105 cycles. Furthermore, it is observed that electroplating defect b alleviates thermal stress within TSVs during temperature cycling. This study provides insights into TSV thermal behavior and reliability, which are crucial for optimizing the design and manufacturing processes of advanced semiconductor packaging. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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14 pages, 2065 KiB  
Article
Prediction of IGBT Gate Oxide Layer’s Performance Degradation Based on MultiScaleFormer Network
by Shilie He, Meiling Yu, Yiqiang Chen, Zhenwei Zhou, Lubin Yu, Chao Zhang and Yuanhua Ni
Micromachines 2024, 15(8), 985; https://doi.org/10.3390/mi15080985 - 30 Jul 2024
Viewed by 525
Abstract
Insulated gate bipolar transistors (IGBTs) are widely used in power electronic devices, and their health prediction problems have attracted much attention in the field of power electronic equipment health management. The performance degradation of IGBT gate oxide is one of the most important [...] Read more.
Insulated gate bipolar transistors (IGBTs) are widely used in power electronic devices, and their health prediction problems have attracted much attention in the field of power electronic equipment health management. The performance degradation of IGBT gate oxide is one of the most important failure modes. In order to analyze this failure mechanism and the ease of implementation of a monitoring circuit, the gate leakage current of IGBTs was selected as the fault precursor parameter for the degradation of their gate oxide performance, and feature selection and fusion were carried out by using time domain characteristic analysis, grayscale correlation, Mahalanobis distance, Kalman filter, and other methods. Thus, a health indicator was obtained to characterize the degradation of IGBT performance, which was used to indicate the degree of aging of the IGBT gate oxide layer. In this paper, we propose an improved degradation prediction model called MultiScaleFormer, inspired by advanced design ideas of the iTransformer network architecture, combined with the health parameters of IGBTs to construct a degradation prediction model for the IGBT gate oxide layer. MultiScaleFormer showed the highest fitting accuracy compared with the Long Short-Term Memory (LSTM), Convolutional Neural Network (CNN), Support Vector Regression (SVR), Gaussian Process Regression (GPR), CNN-LSTM, and Transformer models in our experiment. The mean absolute error (MAE) of the MultiScaleFormer prediction was as low as 0.0087. Extraction of the health indicator and the construction and verification of the degradation prediction model were carried out on the dataset released by the NASA-Ames Laboratory. These results demonstrate the feasibility of the gate leakage current as a fault precursor parameter for IGBT gate oxide failure, and the feasibility and accuracy of the MultiScaleFormer prediction model for IGBT performance degradation. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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17 pages, 7001 KiB  
Article
Optimization of Heat-Dissipation Structure of High-Power Diode Laser in Space Environments
by Lei Cheng, Huaqing Sun, Xuanjun Dai and Bingxing Wei
Micromachines 2024, 15(8), 968; https://doi.org/10.3390/mi15080968 - 29 Jul 2024
Viewed by 550
Abstract
The high-power laser diode (HPLD) has witnessed increasing application in space, as the aerospace industry is developing rapidly. To cope with the space environment, optimizing the heat-dissipation structure and improving the heat-dissipation ability via heat conduction have become key to researching the thermal [...] Read more.
The high-power laser diode (HPLD) has witnessed increasing application in space, as the aerospace industry is developing rapidly. To cope with the space environment, optimizing the heat-dissipation structure and improving the heat-dissipation ability via heat conduction have become key to researching the thermal reliability of the HPLD in space environments. Based on a theoretical analysis of the HPLD, a simulation model of the HPLD was constructed for numerical simulation, and it was found that the maximum temperature and thermal resistance of lasers were efficaciously decreased by changing the packaging position of laser bars. The packaging position of the bars and the cutting angle of the microchannel heat sink (MCHS) were determined based on the light-emitting angle of the light-emitting unit and the internal structure of the MCHS. The internal structure of the MCHS was optimized through a single-factor experiment, an orthogonal experiment, and the combination of neural networks and genetic algorithms (GAs), using three key structural parameters, namely the MCHS ridge width, W1, the channel width, W2, and the channel length, L1. After optimization, the performance of the MCHS was obviously improved. Finally, an analysis was carried out on the applicability of the optimized MCHS to bars with a higher power. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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14 pages, 7440 KiB  
Article
A 25 Mbps 15 ns Propagation Delay 150 kV/μs CMTI Configurable Dual-Channel Capacitive Digital Isolation Driver
by Yuan Zhao, Liang Wang, Zhifeng Chen, Boyang Li, Ronghua Zheng and Chengying Chen
Micromachines 2024, 15(7), 811; https://doi.org/10.3390/mi15070811 - 21 Jun 2024
Viewed by 673
Abstract
Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios [...] Read more.
Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios is proposed with a high common-mode transient immunity (CMTI) and high data transmission rate. The on–off keying (OOK) modulation technique is used to ensure a high speed and accurate signal transmission. A fully integrated high-voltage level-shift driver with an ns-scale delay is proposed for increasing the drive capacity. Post-simulation results in Cadence IC 6.1.7 with the standard 0.18 μm CMOS process show that the proposed architecture achieves a 25 Mbps data transmission rate and 15 ns typical propagation delay with output peak currents of 2 A/4 A, respectively. Meanwhile, a CMTI of more than 150 kV/μs is realized. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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14 pages, 10905 KiB  
Article
A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures
by Li Liu, Jingqi Guo, Yiheng Shi, Kai Zeng and Gangpeng Li
Micromachines 2024, 15(6), 772; https://doi.org/10.3390/mi15060772 - 9 Jun 2024
Viewed by 909
Abstract
This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their [...] Read more.
This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters’ degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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17 pages, 4747 KiB  
Article
Reliability Study of Metal-Oxide Semiconductors in Integrated Circuits
by Boris V. Malozyomov, Nikita V. Martyushev, Natalia Nikolaevna Bryukhanova, Viktor V. Kondratiev, Roman V. Kononenko, Pavel P. Pavlov, Victoria V. Romanova and Yuliya I. Karlina
Micromachines 2024, 15(5), 561; https://doi.org/10.3390/mi15050561 - 24 Apr 2024
Viewed by 883
Abstract
This paper is devoted to the study of CMOS IC parameter degradation during reliability testing. The paper presents a review of literature data on the issue of the reliability of semiconductor devices and integrated circuits and the types of failures leading to the [...] Read more.
This paper is devoted to the study of CMOS IC parameter degradation during reliability testing. The paper presents a review of literature data on the issue of the reliability of semiconductor devices and integrated circuits and the types of failures leading to the degradation of IC parameters. It describes the tests carried out on the reliability of controlled parameters of integrated circuit TPS54332, such as quiescent current, quiescent current in standby mode, resistance of the open key, and instability of the set output voltage in the whole range of input voltages and in the whole range of load currents. The calculated values of activation energies and acceleration coefficients for different test temperature regimes are given. As a result of the work done, sample rejection tests have been carried out on the TPS54332 IC under study. Experimental fail-safe tests were carried out, with subsequent analysis of the chip samples by the controlled parameter quiescent current. On the basis of the obtained experimental values, the values of activation energy and acceleration coefficient at different temperature regimes were calculated. The dependencies of activation energy and acceleration coefficient on temperature were plotted, which show that activation energy linearly increases with increasing temperature, while the acceleration coefficient, on the contrary, decreases. It was also found that the value of the calculated activation energy of the chip is 0.1 eV less than the standard value of the activation energy. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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14 pages, 5343 KiB  
Article
A Method for Automatically Predicting the Radiation-Induced Vulnerability of Unit Integrated Circuits
by Rui Dong, Hongliang Lu, Caozhen Yang, Yutao Zhang, Ruxue Yao, Yujian Wang and Yuming Zhang
Micromachines 2024, 15(4), 541; https://doi.org/10.3390/mi15040541 - 18 Apr 2024
Cited by 1 | Viewed by 864
Abstract
With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with [...] Read more.
With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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14 pages, 6292 KiB  
Article
The Study on Single-Event Effects and Hardening Analysis of Frequency Divider Circuits Based on InP HBT Process
by Xiaohong Zhao, Yongbo Su, You Chen, Yihao Zhang, Jianjun Xiang, Siyi Cheng and Yurong Bai
Micromachines 2024, 15(4), 527; https://doi.org/10.3390/mi15040527 - 15 Apr 2024
Viewed by 896
Abstract
The single-event effects (SEEs) of frequency divider circuits and the radiation tolerance of the hardened circuit are studied in this paper. Based on the experimental results of SEEs in InP HBTs, a transient current model for sensitive transistors is established, taking into account [...] Read more.
The single-event effects (SEEs) of frequency divider circuits and the radiation tolerance of the hardened circuit are studied in this paper. Based on the experimental results of SEEs in InP HBTs, a transient current model for sensitive transistors is established, taking into account the influence of factors such as laser energy, base-collector junction voltage, and radiation position. Moreover, the SEEs of the (2:1) static frequency divider circuit with the InP DHBT process are simulated under different laser energies by adding the transient current model at sensitive nodes. The effect of the time relationship between the pulsed laser and clock signal are discussed. Changes in differential output voltage and the degradation mechanism of unhardened circuits are analyzed, which are mainly attributed to the cross-coupling effect between the transistors in the differential pair. Furthermore, the inverted output is directly connected to the input, leading to a feedback loop and causing significant logic upsets. Finally, an effective hardened method is proposed to provide redundancy and mitigate the impacts of SEEs on the divider. The simulation results demonstrate a notable improvement in the radiation tolerance of the divider. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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14 pages, 5652 KiB  
Article
Design of Inner Matching Three-Stage High-Power Doherty Power Amplifier Based on GaN HEMT Model
by Renyi Li, Chen Ge, Chenwei Liang and Shichang Zhong
Micromachines 2024, 15(3), 388; https://doi.org/10.3390/mi15030388 - 13 Mar 2024
Viewed by 1066
Abstract
This paper introduces the structure and characteristics of an internal-matching high-power Doherty power amplifier based on GaN HEMT devices with 0.25 μm process platforms from the Nanjing Electronic Devices Institute. Through parameter extraction and load-pull testing of the model transistor, an EE_HEMT model [...] Read more.
This paper introduces the structure and characteristics of an internal-matching high-power Doherty power amplifier based on GaN HEMT devices with 0.25 μm process platforms from the Nanjing Electronic Devices Institute. Through parameter extraction and load-pull testing of the model transistor, an EE_HEMT model for the 1.2 mm gate-width GaN HEMT device was established. This model serves as the foundation for designing a high-power three-stage Doherty power amplifier. The amplifier achieved a saturated power gain exceeding 9 dB in continuous wave mode, with a saturated power output of 49.7 dBm. The drain efficiency was greater than 65% at 2.6 GHz. At 9 dB power back-off point, corresponding to an output power of 40.5 dBm, the drain efficiency remained above 55%. The performance of the amplifier remains consistent within the 2.55–2.62 GHz frequency range. The measured power, efficiency, and gain of the designed Doherty power amplifier align closely with the simulation results based on the EE_HEMT model, validating the accuracy of the established model. Furthermore, the in-band matching design reduces the size and weight of the amplifier. The amplifier maintains normal operation even after high and low-temperature testing, demonstrating its reliability. In conjunction with DPD (digital pre-distortion) for the modulated signal test, the amplifier exhibits extremely high linearity (ACLR < −50.93 dBc). This Doherty power amplifier holds potential applications in modern wireless communication scenarios. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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Review

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22 pages, 9997 KiB  
Review
Review of Integrated Gate Driver Circuits in Active Matrix Thin-Film Transistor Display Panels
by Min-Kyu Chang, Seoyeong Jeong, Darren Kim and Hyoungsik Nam
Micromachines 2024, 15(7), 823; https://doi.org/10.3390/mi15070823 - 25 Jun 2024
Viewed by 1020
Abstract
Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes [...] Read more.
Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control. Full article
(This article belongs to the Special Issue High-Reliability Semiconductor Devices and Integrated Circuits, 2nd Edition)
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