Micromachines

Research

13 pages, 1244 KiB

Open AccessArticle

Conductance-Aware Quantization Based on Minimum Error Substitution for Non-Linear-Conductance-State Tolerance in Neural Computing Systems

by Chenglong Huang, Nuo Xu, Wenqing Wang, Yihong Hu and Liang Fang

Micromachines 2022, 13(5), 667; https://doi.org/10.3390/mi13050667 - 24 Apr 2022

Cited by 1 | Viewed by 1977

Abstract

Emerging resistive random-access memory (ReRAM) has demonstrated great potential in the achievement of the in-memory computing paradigm to overcome the well-known “memory wall” in current von Neumann architecture. The ReRAM crossbar array (RCA) is a promising circuit structure to accelerate the vital multiplication-and-accumulation [...] Read more.

Emerging resistive random-access memory (ReRAM) has demonstrated great potential in the achievement of the in-memory computing paradigm to overcome the well-known “memory wall” in current von Neumann architecture. The ReRAM crossbar array (RCA) is a promising circuit structure to accelerate the vital multiplication-and-accumulation (MAC) operations in deep neural networks (DNN). However, due to the nonlinear distribution of conductance levels in ReRAM, a large deviation exists in the mapping process when the trained weights that are quantized by linear relationships are directly mapped to the nonlinear conductance values from the realistic ReRAM device. This deviation degrades the inference accuracy of the RCA-based DNN. In this paper, we propose a minimum error substitution based on a conductance-aware quantization method to eliminate the deviation in the mapping process from the weights to the actual conductance values. The method is suitable for multiple ReRAM devices with different non-linear conductance distribution and is also immune to the device variation. The simulation results on LeNet5, AlexNet and VGG16 demonstrate that this method can vastly rescue the accuracy degradation from the non-linear resistance distribution of ReRAM devices compared to the linear quantization method. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

10 pages, 2811 KiB

Open AccessArticle

Vacuum and Low-Temperature Characteristics of Silicon Oxynitride-Based Bipolar RRAM

by Nayan C. Das, Minjae Kim, Sung-Min Hong and Jae-Hyung Jang

Micromachines 2022, 13(4), 604; https://doi.org/10.3390/mi13040604 - 12 Apr 2022

Cited by 4 | Viewed by 2439

Abstract

This study investigates the switching characteristics of the silicon oxynitride (SiO_xN_y)-based bipolar resistive random-access memory (RRAM) devices at different operating ambiances at temperatures ranging from 300 K to 77 K. The operating ambiances (open air or vacuum) and temperature [...] Read more.

This study investigates the switching characteristics of the silicon oxynitride (SiO_xN_y)-based bipolar resistive random-access memory (RRAM) devices at different operating ambiances at temperatures ranging from 300 K to 77 K. The operating ambiances (open air or vacuum) and temperature affect the device’s performance. The electroforming-free multilevel bipolar Au/Ni/SiO_xN_y/p⁺-Si RRAM device (in open-air) becomes bilevel in a vacuum with an on/off ratio >10⁴ and promising data retention properties. The device becomes more resistive with cryogenic temperatures. The experimental results indicate that the presence and absence of moisture (hydrogen and hydroxyl groups) in open air and vacuum, respectively, alter the elemental composition of the amorphous SiO_xN_y active layer and Ni/SiO_xN_y interface region. Consequently, this affects the overall device performance. Filament-type resistive switching and trap-controlled space charge limited conduction (SCLC) mechanisms in the bulk SiO_xN_y layer are confirmed. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

7 pages, 1742 KiB

Open AccessArticle

Reflow Soldering Capability Improvement by Utilizing TaN Interfacial Layer in 1Mbit RRAM Chip

by Peng Yuan, Danian Dong, Xu Zheng, Guozhong Xing and Xiaoxin Xu

Micromachines 2022, 13(4), 567; https://doi.org/10.3390/mi13040567 - 31 Mar 2022

Cited by 1 | Viewed by 1930

Abstract

We investigated the thermal stability of a 1Mbit OxRRAM array embedded in 28 nm COMS technology. A back-end-of-line (BEOL) solution with a TaN–Ta interfacial layer was proposed to eliminate the failure rate after reflow soldering assembly at 260 °C. By utilizing a TaN–Ta [...] Read more.

We investigated the thermal stability of a 1Mbit OxRRAM array embedded in 28 nm COMS technology. A back-end-of-line (BEOL) solution with a TaN–Ta interfacial layer was proposed to eliminate the failure rate after reflow soldering assembly at 260 °C. By utilizing a TaN–Ta interfacial layer (IL), the oxygen defects in conductive filament were redistributed, and electromigration lifetimes of Cu-based damascene interconnects were improved, which contributed to optimization. This work provides a potential solution for the practical application of embedded RRAM beyond the 28 nm technology node. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

11 pages, 3793 KiB

Open AccessArticle

Hardware Demonstration of SRDP Neuromorphic Computing with Online Unsupervised Learning Based on Memristor Synapses

by Ruiyi Li, Peng Huang, Yulin Feng, Zheng Zhou, Yizhou Zhang, Xiangxiang Ding, Lifeng Liu and Jinfeng Kang

Micromachines 2022, 13(3), 433; https://doi.org/10.3390/mi13030433 - 11 Mar 2022

Cited by 11 | Viewed by 3577

Abstract

Neuromorphic computing has shown great advantages towards cognitive tasks with high speed and remarkable energy efficiency. Memristor is considered as one of the most promising candidates for the electronic synapse of the neuromorphic computing system due to its scalability, power efficiency and capability [...] Read more.

Neuromorphic computing has shown great advantages towards cognitive tasks with high speed and remarkable energy efficiency. Memristor is considered as one of the most promising candidates for the electronic synapse of the neuromorphic computing system due to its scalability, power efficiency and capability to simulate biological behaviors. Several memristor-based hardware demonstrations have been explored to achieve the capacity of unsupervised learning with the spike-rate-dependent plasticity (SRDP) learning rule. However, the learning capacity is limited and few of the memristor-based hardware demonstrations have explored the online unsupervised learning at the network level with an SRDP algorithm. Here, we construct a memristor-based hardware system and demonstrate the online unsupervised learning of SRDP networks. The neuromorphic system consists of multiple memristor arrays as the synapse and the discrete CMOS circuit unit as the neuron. Unsupervised learning and online weight update of 10 MNIST handwritten digits are realized by the constructed SRDP networks, and the recognition accuracy is above 90% with 20% device variation. This work paves the way towards the realization of large-scale and efficient networks for more complex tasks. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

8 pages, 2048 KiB

Open AccessArticle

Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array

by Jie Yu, Woyu Zhang, Danian Dong, Wenxuan Sun, Jinru Lai, Xu Zheng, Tiancheng Gong, Yi Li, Dashan Shang, Guozhong Xing and Xiaoxin Xu

Micromachines 2022, 13(2), 308; https://doi.org/10.3390/mi13020308 - 17 Feb 2022

Cited by 3 | Viewed by 2101

Abstract

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly [...] Read more.

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 10⁵ s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

14 pages, 725 KiB

Open AccessArticle

A Novel RFID Authentication Protocol Based on Reconfigurable RRAM PUF

by Qirui Ren, Xiangqu Fu, Hao Wu, Kaiqi Yang, Dengyun Lei, Guozhong Xing and Feng Zhang

Micromachines 2021, 12(12), 1560; https://doi.org/10.3390/mi12121560 - 15 Dec 2021

Cited by 4 | Viewed by 2432

Abstract

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries. Aiming at the current light-weight RFID encryption scheme with limited information protection methods, combined with the physical unclonable function (PUF) composed of resistive random access memory (RRAM), a new type [...] Read more.

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries. Aiming at the current light-weight RFID encryption scheme with limited information protection methods, combined with the physical unclonable function (PUF) composed of resistive random access memory (RRAM), a new type of high-efficiency reconfigurable strong PUF circuit structure is proposed in this paper. Experimental results show that the proposed PUF shows an almost ideal value (50%) of inter-chip hamming distance (HD) (µ/

σ

= 0.5001/0.0340) among 1000 PUF keys, and intra-chip HD results are very close to the ideal value (0). The bit error rate (BER) is as low as

3.8 \times 10^{- 6}

across one million challenges. Based on the RRAM PUF, we propose and implement a light weight RFID authentication protocol. By virtue of RRAM’s model ability, the protocol replaces the One-way Hash Function with a response chain mutual encryption algorithm. The results of test and analysis show that the protocol can effectively resist multiple threats such as physical attacks, replay attacks, tracking attacks and asynchronous attacks, and has good stability. At the same time, based on RRAM’s unique resistance variability, PUF also has the advantage of being reconfigurable, providing good security for RFID tags. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

15 pages, 520 KiB

Open AccessArticle

A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

by Stefan Pechmann, Timo Mai, Julian Potschka, Daniel Reiser, Peter Reichel, Marco Breiling, Marc Reichenbach and Amelie Hagelauer

Micromachines 2021, 12(11), 1277; https://doi.org/10.3390/mi12111277 - 20 Oct 2021

Cited by 7 | Viewed by 2425

Abstract

Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the [...] Read more.

Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the individual neurons. This paper introduces a memory block using resistive memory cells (RRAM) to realize this weight and bias storage in an embedded and distributed way while also offering programming and multi-level ability. By implementing power gating, overall power consumption is decreased significantly without data loss by taking advantage of the non-volatility of the RRAM technology. Due to the versatility of the peripheral circuitry, the presented memory concept can be adapted to different applications and RRAM technologies. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

17 pages, 2927 KiB

Open AccessArticle

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

by Tommaso Zanotti, Paolo Pavan and Francesco Maria Puglisi

Micromachines 2021, 12(10), 1243; https://doi.org/10.3390/mi12101243 - 14 Oct 2021

Cited by 7 | Viewed by 2272

Abstract

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel [...] Read more.

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 10⁸) and energy-delay product (projected up to a factor of 10¹⁰). Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

7 pages, 2188 KiB

Open AccessArticle

Study on Cross-Coupled-Based Sensing Circuits for Nonvolatile Flip-Flops Operating in Near/Subthreshold Voltage Region

by Taehui Na

Micromachines 2021, 12(10), 1177; https://doi.org/10.3390/mi12101177 - 29 Sep 2021

Cited by 1 | Viewed by 1873

Abstract

To date, most studies focus on complex designs to realize offset cancelation characteristics in nonvolatile flip-flops (NV-FFs). However, complex designs using switches are ineffective for offset cancelation in the near/subthreshold voltage region because switches become critical contributors to the offset voltage. To address [...] Read more.

To date, most studies focus on complex designs to realize offset cancelation characteristics in nonvolatile flip-flops (NV-FFs). However, complex designs using switches are ineffective for offset cancelation in the near/subthreshold voltage region because switches become critical contributors to the offset voltage. To address this problem, this paper proposes a novel cross-coupled NMOS-based sensing circuit (CCN-SC) capable of improving the restore yield, based on the concept that the simplest is the best, of an NV-FF operating in the near/subthreshold voltage region. Measurement results using a 65 nm test chip demonstrate that with the proposed CCN-SC, the restore yield is increased by more than 25 times at a supply voltage of 0.35 V, compared to that with a cross-coupled inverter-based SC, at the cost of 18× higher power consumption. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

13 pages, 4870 KiB

Open AccessArticle

Enhancing the Data Reliability of Multilevel Storage in Phase Change Memory with 2T2R Cell Structure

by Yi Lv, Qian Wang, Houpeng Chen, Chenchen Xie, Shenglan Ni, Xi Li and Zhitang Song

Micromachines 2021, 12(9), 1085; https://doi.org/10.3390/mi12091085 - 9 Sep 2021

Cited by 2 | Viewed by 2043

Abstract

Multilevel storage and the continuing scaling down of technology have significantly improved the storage density of phase change memory, but have also brought about a challenge, in that data reliability can degrade due to the resistance drift. To ensure data reliability, many read [...] Read more.

Multilevel storage and the continuing scaling down of technology have significantly improved the storage density of phase change memory, but have also brought about a challenge, in that data reliability can degrade due to the resistance drift. To ensure data reliability, many read and write operation technologies have been proposed. However, they only mitigate the influence on data through read and write operations after resistance drift occurs. In this paper, we consider the working principle of multilevel storage for PCM and present a novel 2T2R structure circuit to increase the storage density and reduce the influence of resistance drift fundamentally. To realize 3-bit per cell storage, a wide range of resistances were selected as different states of phase change memory. Then, we proposed a 4:3 compressing encoding scheme to transform the output data into binary data states. Therefore, the designed 2T2R was proven to have optimized storage density and data reliability by monitoring the conductance distribution at four time points (1 ms, 1 s, 6 h, 12 h) in 4000 devices. Simulation results showed that the resistance drift of our proposed 2T2R structure can significantly improve the storage density of multilevel storage and increase the data reliability of phase change memory. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

10 pages, 2423 KiB

Open AccessArticle

Electroforming-Free Bipolar Resistive Switching Memory Based on Magnesium Fluoride

by Nayan C. Das, Minjae Kim, Jarnardhanan R. Rani, Sung-Min Hong and Jae-Hyung Jang

Micromachines 2021, 12(9), 1049; https://doi.org/10.3390/mi12091049 - 30 Aug 2021

Cited by 8 | Viewed by 2333

Abstract

Electroforming-free resistive switching random access memory (RRAM) devices employing magnesium fluoride (MgF_x) as the resistive switching layer are reported. The electroforming-free MgF_x based RRAM devices exhibit bipolar SET/RESET operational characteristics with an on/off ratio higher than 10² and good [...] Read more.

Electroforming-free resistive switching random access memory (RRAM) devices employing magnesium fluoride (MgF_x) as the resistive switching layer are reported. The electroforming-free MgF_x based RRAM devices exhibit bipolar SET/RESET operational characteristics with an on/off ratio higher than 10² and good data retention of >10⁴ s. The resistive switching mechanism in the Ti/MgF_x/Pt devices combines two processes as well as trap-controlled space charge limited conduction (SCLC), which is governed by pre-existing defects of fluoride vacancies in the bulk MgF_x layer. In addition, filamentary switching mode at the interface between the MgF_x and Ti layers is assisted by O–H group-related defects on the surface of the active layer. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

11 pages, 2514 KiB

Open AccessArticle

Analysis of Leakage Current of HfO₂/TaO_x-Based 3-D Vertical Resistive Random Access Memory Array

by Zhisheng Chen, Renjun Song, Qiang Huo, Qirui Ren, Chenrui Zhang, Linan Li and Feng Zhang

Micromachines 2021, 12(6), 614; https://doi.org/10.3390/mi12060614 - 26 May 2021

Cited by 3 | Viewed by 3232

Abstract

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM [...] Read more.

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

15 pages, 1029 KiB

Open AccessArticle

Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

by Zhongjian Bian, Xiaofeng Hong, Yanan Guo, Lirida Naviner, Wei Ge and Hao Cai

Micromachines 2021, 12(5), 551; https://doi.org/10.3390/mi12050551 - 12 May 2021

Cited by 5 | Viewed by 3024

Abstract

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet [...] Read more.

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory)

► Show Figures

Figure 1

Journal Menu

Journal Browser

Advances in Emerging Nonvolatile Memory

Share This Special Issue

Special Issue Editor

Special Issue Information

Keywords

Benefits of Publishing in a Special Issue

Related Special Issues

Published Papers (13 papers)

Research

Further Information

Guidelines

MDPI Initiatives

Follow MDPI