Search Results (528)

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications. Full article

This study presents a hard-switching full-bridge DC-DC converter with synchronous rectification based on Gallium Nitride (GaN) transistors to evaluate the advantages of GaN devices in power supplies. In comparison to traditional silicon-based devices, GaN transistors are utilized in both the primary and secondary stages of the converter, exploiting GaN’s lower on-resistance to enhance performance. The converter operates at a switching frequency of 300 kHz, with an input voltage range of 36 V to 75 V, delivering an output of 28 V/42 A. Experimental results show that the GaN-based converter achieves an output power of 1176 W within standard half-brick package dimensions. The measured peak efficiency is 97.1%, and the power density reaches 430 W/in³. These findings demonstrate that GaN-based converters offer superior efficiency and power density compared to conventional silicon-based designs, making them highly suitable for aerospace, automotive, and communication power supplies. Full article

A family of improved low-voltage switched-capacitor circuits is introduced. It is based on the utilization of multiple-output class AB/AB op-amp architectures that provide true sample and hold outputs that are not subject to a reset phase as with conventional switched-capacitor circuits. This feature essentially relaxes the op-amp slew rate requirements, allowing a higher speed and simple low-voltage operation. A power-efficient GB boosting technique based on resistive local common mode feedback is used to significantly improve the GB and internal/external slew rate of the op-amps with only a 36.5% additional power dissipation. Full article

MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibration to be accurate enough. In this paper, a charge pump phase-locked loop-based frequency conditioning method for MEMS resonators is explored. An optimization scheme is proposed to enhance the frequency stability and signal quality of MEMS resonators. The experimental results show that the method significantly improves the resonator performance and achieves effective control of the resonant frequency. This research provides a new technical path for the design of high-performance MEMS oscillators, which has important theoretical significance and practical application value. Full article

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient memory utilization essential. This article presents key design concepts for developing an efficient, lightweight, and reliable embedded filesystem. It introduces an improved version of the configurable flash filesystem (CFFS), designed to maximize memory utilization, minimize flash wear, and support portability across hardware platforms and operating systems. Reliability mechanisms integrated into CFFS are also discussed. We compare CFFS with widely used low-power embedded filesystems—LittleFS, SPIFFS, and FDS—highlighting its advantages in memory efficiency and reduced flash memory wear. Experimental results demonstrate that CFFS achieves up to 99% memory utilization while significantly reducing erase operations. Full article

Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means clustering, one of the more widely used unsupervised machine learning algorithms. The k-means algorithm partitions data into k clusters, where k also denotes the number of centroids, with each centroid representing the center of a cluster. The clustering process involves assigning each data point to the nearest centroid by minimizing the within-cluster sum of squares (WCSS), a key metric used to evaluate clustering quality. A lower WCSS value signifies better clustering. Conventionally, WCSS is computed with high precision using an accurate adder. In this paper, we investigate the impact of employing various approximate adders for WCSS computation and compare their results against those obtained with an accurate adder. Further, we propose a new approximate adder (NAA) in this paper. To assess its effectiveness, we utilize it for the k-means clustering of some publicly available artificial datasets with varying levels of complexity, and compare its performance with the accurate adder and many other approximate adders. The experimental results confirm the efficacy of NAA in clustering, as NAA yields WCSS values that closely match or are identical to those obtained using the accurate adder. We also implemented hardware designs of accurate and approximate adders using a 28 nm CMOS standard cell library. The design metrics estimated show that NAA achieves a 37% reduction in delay, a 22% reduction in area, and a 31% reduction in power compared to the accurate adder. In terms of the power-delay product that serves as a representative metric for energy efficiency, NAA reports a 57% reduction compared to the accurate adder. In terms of the area-delay product that serves as a representative metric for design efficiency, NAA reports a 51% reduction compared to the accurate adder. NAA also outperforms several existing approximate adders in terms of design metrics while preserving clustering effectiveness. Full article

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB. Full article

Wireless sensor networks are at the center of scientific interest thanks to their ever-growing range of applications. The main weakness of wireless sensor networks is the restricted lifetime of their sensor nodes due to limited energy capacity. The extension of the lifespan of sensor nodes is pursued in various ways. One of them is the usage of protocols that achieve energy-efficient routing. LEACH is one of the pioneering protocols of this type and has numerous descendants. This research article focuses on energy-efficient routing protocols that are based on LEACH. Specifically, a study of LEACH along with many of its successors is provided. In addition, a novel protocol of this kind, named T-LEACH_SAS is introduced. This protocol combines the threshold-based approach for selecting cluster heads that was first introduced in T-LEACH, which is a well-known protocol, along with a mechanism for sleep–awake scheduling. The performance of T-LEACH_SAS is compared against that of both LEACH and T-LEACH via simulation tests that confirm that T-LEACH_SAS indeed provides a promising choice for energy-efficient routing in WSNs. Full article

This paper proposes a miniaturized frequency-scanning antenna with high scanning rate. To overcome the OSB (open stopband) of traditional leaky wave antenna, CRLH-TL (Composite Right/Left-Handed-Transmission Line) is adopted. Furthermore, an antenna unit consisting of two symmetrically curved microstrip lines with two short branches is employed, whose second mode exhibits excellent transmission characteristics. The measurements demonstrate that the antenna can achieve scanning from −67.5° to 35.5° in the frequency band range of 5.65–6.5 GHz, with a scanning rate of 7.3. During scanning, the highest gain in the band is 12.3 dBi, the lowest is 10 dBi, and the gain fluctuation is within 2.3 dB, showing good scanning characteristics. Additionally, the length of the proposed antenna is approximately 3.84λ₀ for a central frequency of 5.95 GHz. Full article

In a photovoltaic power enhancer system, when it is operated in current-control mode, significant nonuniform temperature distribution occurs in the converter due to thermal coupling effects, dissipative boundary conditions, and differences in device losses within the in-phase bridge. Accurate on-site estimation of the power device’s junction temperature is critical in the system design. To address this problem, a novel thermal behavior estimation model based on electro-thermal analysis is proposed in this paper, which can be used for asymmetric power MOSFETs in a photovoltaic power enhancer system. Thermal coupling effects and dissipative boundary conditions are, firstly, analyzed in a three-dimensional finite element model. A coupling impedance matrix is constructed through step power response extraction to describe the significant thermal coupling effects among devices. The complete heat sink is decoupled into several sub-parts representing different dissipative boundary conditions. A compact RC network model for estimating junction temperature is established based on the combination of the coupling impedance and the sub-heat-sink impedance. The proposed model is verified by finite element simulation and experimental measurement. Full article

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic computing, inspired by the biological brain, offers a transformative paradigm for addressing these challenges. This review paper provides an overview of advancements in 2D spintronics and device architectures designed for neuromorphic applications, with a focus on techniques such as spin-orbit torque, magnetic tunnel junctions, and skyrmions. Emerging van der Waals materials like CrI₃, Fe₃GaTe₂, and graphene-based heterostructures have demonstrated unparalleled potential for integrating memory and logic at the atomic scale. This work highlights technologies with ultra-low energy consumption (0.14 fJ/operation), high switching speeds (sub-nanosecond), and scalability to sub-20 nm footprints. It covers key material innovations and the role of spintronic effects in enabling compact, energy-efficient neuromorphic systems, providing a foundation for advancing scalable, next-generation computing architectures. Full article

Edge devices execute pre-trained Artificial Intelligence (AI) models optimized on large Graphical Processing Units (GPUs); however, they frequently require fine-tuning when deployed in the real world. This fine-tuning, referred to as edge learning, is essential for personalized tasks such as speech and gesture recognition, which often necessitate the use of recurrent neural networks (RNNs). However, training RNNs on edge devices presents major challenges due to limited memory and computing resources. In this study, we propose a system for RNN training through sequence partitioning using the Forward Propagation Through Time (FPTT) training method, thereby enabling edge learning. Our optimized hardware/software co-design for FPTT represents a novel contribution in this domain. This research demonstrates the viability of FPTT for fine-tuning real-world applications by implementing a complete computational framework for training Long Short-Term Memory (LSTM) networks utilizing FPTT. Moreover, this work incorporates the optimization and exploration of a scalable digital hardware architecture using an open-source hardware-design framework, named Chipyard and its implementation on a Field-Programmable Gate Array (FPGA) for cycle-accurate verification. The empirical results demonstrate that partitioned training on the proposed architecture enables an 8.2-fold reduction in memory usage with only a 0.2× increase in latency for small-batch sequential MNIST (S-MNIST) compared to traditional non-partitioned training. Full article

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with rail-to-rail ICMR features. The NOR2 topology, which is also better than the complementary NAND2-based topology previously presented by the authors, is even able to guarantee improvements in the order of 8× –16× higher speed and 7× lower PDP, with respect to the other rail-to-rail ICMR standard-cell-based topologies in the literature. Concerning the standard-cell oriented design methodology, it is focused on the impact of the cell’s strength, which is the only free parameter, on delay, power consumption, ICMR and offset. The circuit performances are demonstrated for supply voltages equal to 600 mV, 300 mV and 150 mV, considering a 45 nm CMOS technology. Full article

Simple designs of current-mode quadrature oscillators are presented in this work. The main achievement, with regards to the literature, is the minimization of the required transistor count accomplished by the utilization of a suitable lossless integration stage. The derived post-layout simulation results confirm the validity of the presented concept and show that the resulting structure has attractive characteristics in both frequency and time-domain. Full article

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al_0.30Ga_0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and I_ON to I_OFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec. Full article