Search Results (54)

This work presents a novel time-to-digital converter based on the analog sampling of dual-phase periodic signals generated from a free-running oscillator. A proof-of-concept ASIC, implemented in 130 nm CMOS technology, achieves an average single-shot precision of 0.9 ps-rms for time intervals up to 3 ns, with a best performance of 0.79 ps-rms. It maintains a precision below 3.7 ps-rms for intervals up to 25 ns. The design demonstrates excellent linearity, with a peak-to-peak differential nonlinearity of 0.56 LSB and a peak-to-peak integral nonlinearity of 1.43 LSB. The free-running oscillator is shareable across multiple channels, enabling power consumption of approximately 4.1 mW per channel and efficient area utilization. These features make the design highly suitable for detection systems requiring picosecond-level precision and high channel density, such as silicon pixel sensors, SPADs, LiDARs, and time-correlated single-photon counting systems. Furthermore, the architecture shows strong potential for use in high-count-rate applications, reaching up to 22 Mcps. Full article

Single-photon avalanche detectors (SPADs) have significant applications in fields such as autonomous driving. However, processing massive amounts of background data requires substantial storage and computational resources. This paper designs a linear SPAD sensor capable of three detection modes: 2D intensity detection, 3D synchronous detection, and 3D asynchronous detection. A configurable coincidence circuit is used to effectively suppress background light. To overcome the significant resource demands for storage and computation, this paper designs a histogram circuit that simultaneously possesses data storage and shifting capabilities. This circuit can not only perform statistical counting on time data but also shift data to quickly complete computational analysis. The chip is fabricated using a 0.13 μm mixed-signal CMOS process, with a pixel scale of 64 elements, a time resolution of 132 ps, and a power consumption of 12.9 mW. Test results indicate that the chip has good detection capabilities and good background light suppression. When the background light intensity is 6000 lux, the maximum background data are suppressed by 95.4%, and the average suppression rate increases to 86% as the coincidence threshold is raised from 0 to 1. Full article

Single-Photon Avalanche Photodiodes (SPADs) are increasingly utilized in high-temperature-operated, high-performance Light Detection and Ranging (LiDAR) systems as well as in ultra-low-temperature-operated quantum science applications due to their high photon sensitivity and timing resolution. Consequently, the jitter value of SPADs at different temperatures plays a crucial role in LiDAR systems and Quantum Key Distribution (QKD) applications. However, limited studies have been conducted on this topic. In this study, we analyze the jitter characteristics of SPAD devices, focusing on the influence of device structures in two SPAD designs fabricated using the TSMC 18HV and TSMC 13HV processes. Using picosecond lasers with wavelengths ranging from ultraviolet (405 nm) to near-infrared (905 nm), we investigate the impact of different diffusion carrier types on jitter values and their temperature dependence across a range of 0 °C to 60 °C. Our results show that the jitter value of SPAD devices with low electric field regions varies significantly with temperature. This variation can be attributed to the higher temperature-dependent diffusion constant, as demonstrated by fitting the jitter diffusion tail with two diffusion time constants. In contrast, SPADs designed with modified electric field distributions exhibit smaller diffusion time constants and weaker temperature dependence, resulting in a much smaller temperature-dependent jitter value. Full article

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD chip and a gating chip, are eliminated by the integration. The gating voltage transients of the SPAD are measured using an integrated mini-pad and a picoprobe. Furthermore, the gating voltage transients of a CMOS gating circuit and of the BiCMOS gating circuit are compared for the same integrated SPAD. The extension of the 0.35 $\mathsf{\mu }$m CMOS process by an NPN transistor process module enabled the BiCMOS gating circuit. The avalanche build-up time of the SPAD is reduced to 1.6 ns due to the integration compared to about 3 ns for a wire-bonded off-chip SPAD using the same ${\mathrm{n}}^{+}$ and p-well as well as the same 0.35 $\mathsf{\mu }$m technology. Full article

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.3 µm × 36.5 µm, a notable size reduction compared to conventional designs. The experimental results demonstrated high performance, with an integral nonlinearity (INL) of 0.35/0.14 least significant bit (LSB) and a differential nonlinearity (DNL) of 0.14/−0.12 LSB. In addition, the proposed TDC can support the construction of histograms comprising up to 512 bins, making it an effective solution to accommodate a wide range of resolution requirements. Validated in a point-of-care (PoC) device for fluorescence lifetime measurements, it distinguished between lifetimes of approximately 4.1 ns, 3.6 ns and 80 ns with the Alexa Fluor (AF) 546 and 568 dyes and Quantum Dot (QD) 705, respectively. The analog storage design and area-efficient architecture offer a novel approach to integrating TDCs in SPAD-based systems, with potential applications in medical diagnostics and beyond. Full article

We present robust pixel design methodologies for a vertical avalanche photodiode-based CMOS image sensor, taking account of three critical practical factors: (i) “guard-ring-free” pixel isolation layout, (ii) device characteristics “insensitive” to applied voltage and temperature, and (iii) stable operation subject to intense light exposure. The “guard-ring-free” pixel design is established by resolving the tradeoff relationship between electric field concentration and pixel isolation. The effectiveness of the optimization strategy is validated both by simulation and experiment. To realize insensitivity to voltage and temperature variations, a global feedback resistor is shown to effectively suppress variations in device characteristics such as photon detection efficiency and dark count rate. An in-pixel overflow transistor is also introduced to enhance the resistance to strong illumination. The robustness of the fabricated VAPD-CIS is verified by characterization of 122 different chips and through a high-temperature and intense-light-illumination operation test with 5 chips, conducted at 125 °C for 1000 h subject to 940 nm light exposure equivalent to 10 kLux. Full article

A single-photon avalanche diode (SPAD) is a photon-counting sensor renowned for its exceptional single-photon sensitivity. One significant feature of SPADs is their non-linear response to light, making them ideal for high-dynamic range imaging applications. In SPAD imaging, the photon detection mode, which depends on the quenching method employed, is crucial for optimizing image quality and dynamic range. This paper examines the free-running and gating imaging modes, evaluating their impacts on photon capture and saturation limits. Given that the number of incident photons follows a Poisson distribution, we introduce an innovative imaging-quenching model based on statistical mathematics. We designed and fabricated two SPAD imaging sensors using 180 nm CMOS technology. Image processing and evaluation were conducted using a mapping method. Our results show that in low-light conditions, the gating mode surpasses the free-running mode in the signal-to-noise ratio (SNR). However, the free-running mode exhibits a saturation limit of more than an order of magnitude higher than that of the gating mode, demonstrating its superior capability to handle a broader range of light intensities. This paper provides a thorough analysis of the differences between the two imaging methods, incorporating the theoretical mathematical model, circuit characteristics, and computed imaging quality. Full article

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR). Full article

A Point-of-Care system for molecular diagnosis (PoC-MD) is described, combining GaN and CMOS chips. The device is a micro-system for fluorescence measurements, capable of analyzing both intensity and lifetime. It consists of a hybrid micro-structure based on a 32 × 32 matrix addressable GaN microLED array, with square LEDs of 50 µm edge length and 100 µm pitch, with an underneath wire bonded custom chip integrating their drivers and placed face-to-face to an array of 16 × 16 single-photon avalanche diodes (SPADs) CMOS. This approach replaces instrumentation based on lasers, bulky optical components, and discrete electronics with a full hybrid micro-system, enabling measurements on 32 × 32 spots. The reported system is suitable for long lifetime (>10 ns) fluorophores with a limit of detection ~1/4 µM. Proof-of-concept measurements of streptavidin conjugate Qdot™ 605 and Amino PEG Qdot™ 705 are demonstrated, along with the device ability to detect both fluorophores in the same measurement. Full article

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (V_GS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (V_GS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length L_eff = 0.25 µm and a SiO₂ gate-oxide thickness T_ox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage V_DDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients. Full article

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 10⁸ MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO₂ interface trap generated by ionization. Full article

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found. Full article

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (I_d) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to I_d degradation including increased off-state current (I_off) and decreased on-state current (I_on). The increased I_off further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. Full article

We present the first reported use of a CMOS-compatible single photon avalanche diode (SPAD) array for the detection of high-energy charged particles, specifically pions, using the Super Proton Synchrotron at CERN, the European Organization for Nuclear Research. The results confirm the detection of incident high-energy pions at 120 GeV, minimally ionizing, which complements the variety of ionizing radiation that can be detected with CMOS SPADs. Full article

Light detection and ranging (LiDAR) technology, a cutting-edge advancement in mobile applications, presents a myriad of compelling use cases, including enhancing low-light photography, capturing and sharing 3D images of fascinating objects, and elevating the overall augmented reality (AR) experience. However, its widespread adoption has been hindered by the prohibitive costs and substantial power consumption associated with its implementation in mobile devices. To surmount these obstacles, this paper proposes a low-power, low-cost, single-photon avalanche detector (SPAD)-based system-on-chip (SoC) which packages the microlens arrays (MLAs) and a lightweight RGB-guided sparse depth imaging completion neural network for 3D LiDAR imaging. The proposed SoC integrates an 8 × 8 SPAD macropixel array with time-to-digital converters (TDCs) and a charge pump, fabricated using a 180 nm bipolar-CMOS-DMOS (BCD) process. Initially, the primary function of this SoC was limited to serving as a ranging sensor. A random MLA-based homogenizing diffuser efficiently transforms Gaussian beams into flat-topped beams with a 45° field of view (FOV), enabling flash projection at the transmitter. To further enhance resolution and broaden application possibilities, a lightweight neural network employing RGB-guided sparse depth complementation is proposed, enabling a substantial expansion of image resolution from 8 × 8 to quarter video graphics array level (QVGA; 256 × 256). Experimental results demonstrate the effectiveness and stability of the hardware encompassing the SoC and optical system, as well as the lightweight features and accuracy of the algorithmic neural network. The state-of-the-art SoC-neural network solution offers a promising and inspiring foundation for developing consumer-level 3D imaging applications on mobile devices. Full article