Search Results (27)

Memristor-based neuromorphic computing offers a promising pathway for efficient in-memory processing. However, the scalability and reliability of such systems are severely compromised by parasitic resistances (including line and input resistances) in crossbar arrays, which cause significant IR-drop during vector–matrix multiplication (VMM). Existing research often suffers from high computational latency or relies on the precise extraction of parasitic parameters, which is impractical and computationally expensive for large-scale integration. To overcome these limitations, we propose a Parameter-Agnostic Adaptive Compensation (PAAC) method based on a distributed linear approximation model. By analyzing the circuit characteristics, we conquered the challenge of coupling between parasitic effects and output current, deriving a simplified linear relationship that requires no prior knowledge of specific resistance values. The PAAC method involves only a single-step pre-calibration experiment to determine a global compensation factor, achieving an ultra-low computational complexity during inference. We validated the method using a comprehensive two-stage strategy: board-level hardware experiments confirmed its feasibility by reducing current distortion from 71% to 2%, while extensive large-scale HSPICE simulations verified its scalability, restoring classification accuracy from 89% to 95%. This work provides a robust, low-overhead solution that eliminates the dependency on precise parameter modeling, facilitating the realization of large-scale, high-precision neuromorphic hardware. Full article

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence. Full article

Memristors are valuable elements with very good memory and switching features. They have minimal power consumption, nano-scale sizes, and a possibility for integration with high-density Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. They are applicable in neural networks, memory crossbars, and different electronic devices. This work considers some improved and existing models for memristors, functioning at high-frequency signals with a high speed and very good effectiveness. The main parasitic parameters—series resistance, capacitance, and small-signal direct current (DC) voltage and current shifting signals—are taken into account. An additional leakage conductance is analyzed as a parasitic component. The influence of the parasitic parameters on the normal functioning of memristor-based circuits is analyzed and evaluated at hard-switching and soft-switching modes. For investigations of the main characteristics of the considered models and their applicability in memory arrays, Linear Technology Simulation Program with Integrated Circuits Emphasis (LTSPICE) library models are generated and analyzed. The considered models operate at low-, middle- and high-frequency signals, clearly demonstrating the main properties of memristors. Their appropriate operation in passive memory arrays is analyzed and established. The proposed models have a 26% enhanced accuracy in fitting experimental i-v relations. They ensure good memory and switching properties for memory arrays. This work could be a suitable step towards the design and manufacturing of ultra-high-density memristor-based integrated chips. Full article

Memristor crossbar-based neural network systems offer high throughput with low energy consumption. A key advantage of on-chip training in these systems is their ability to mitigate the effects of device variability and faults. This paper presents an efficient on-chip training circuit for memristor crossbar-based multi-layer neural networks. We propose a novel method for storing the product of two analog signals directly in a memristor device, eliminating the need for ADC and DAC converters. Experimental results show that the proposed system is approximately twice as energy efficient and 1.5 times faster than existing memristor-based systems for training multi-layer neural networks. Full article

An ultralow-power, high-performance online-learning and anomaly-detection system has been developed for edge security applications. Designed to support personalized learning without relying on cloud data processing, the system employs sample-wise learning, eliminating the need for storing entire datasets for training. Built using memristor-based analog neuromorphic and in-memory computing techniques, the system integrates two unsupervised autoencoder neural networks—one utilizing optimized crossbar weights and the other performing real-time learning to detect novel intrusions. Threshold optimization and anomaly detection are achieved through a fully analog Euclidean Distance (ED) computation circuit, eliminating the need for floating-point processing units. The system demonstrates 87% anomaly-detection accuracy; achieves a performance of 16.1 GOPS—774× faster than the ASUS Tinker Board edge processor; and delivers an energy efficiency of 783 GOPS/W, consuming only 20.5 mW during anomaly detection. Full article

Local learning algorithms, such as Equilibrium Propagation (EP), have emerged as alternatives to global learning methods like backpropagation for training neural networks. EP offers the potential for more energy-efficient hardware implementation by utilizing only local neuron information for weight updates. However, the practical implementation of EP using memristor-based circuits has significant challenges due to the immature fabrication processes of memristors, resulting in defects and variability issues. Previous implementations of EP with memristor crossbars use two separate circuits for the free and nudge phases. This approach can suffer differences in defects and variability between the two circuits, potentially leading to significant performance degradation. To overcome these limitations, in this paper, we propose a novel time-multiplexing technique that combines the free and nudge phases into a single memristor circuit. Our proposed scheme integrates the dynamic equations of the free and nudge phases into one circuit, allowing defects and variability compensation during the training. Simulations using the MNIST dataset demonstrate that our approach maintains a 92% recognition rate even with a 10% defect rate in memristors, compared to 33% for the previous scheme. Furthermore, the proposed circuit reduces area overhead for both the memristor circuit solving EP’s algorithm and the weight-update control circuit. Full article

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array. Full article

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor–CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network’s controller. Firstly, the input neurons perform preprocessing for the DVS camera’s events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply–Accumulate (MAC) calculations according to the memristor’s current–voltage relationship. The hidden and output neurons can convert the crossbar’s column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network’s controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network’s performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme. Full article

Binary memristor crossbars have great potential for use in brain-inspired neuromorphic computing. The complementary crossbar array has been proposed to perform the Exclusive-NOR function for neuromorphic pattern recognition. The single crossbar obtained by shortening the Exclusive-NOR function has more advantages in terms of power consumption, area occupancy, and fault tolerance. In this paper, we present the impact of data density on the single memristor crossbar architecture for neuromorphic image recognition. The impact of data density on the single memristor architecture is mathematically derived from the reduced formula of the Exclusive-NOR function, and then verified via circuit simulation. The complementary and single crossbar architectures are tested by using ten 32 × 32 images with different data densities of 0.25, 0.5, and 0.75. The simulation results showed that the data density of images has a negative effect on the single memristor crossbar architecture while not affecting the complementary memristor crossbar architecture. The maximum output column current produced by the single memristor crossbar array decreases as data density decreases while the complementary memristor crossbar array architecture provides stable maximum output column currents. When recognizing images with data density as low as 0.25, the maximum output column currents of the single memristor crossbar architecture is reduced four-fold compared with the maximum currents from the complementary memristor crossbar architecture. This reduction causes the Winner-take-all circuit to work incorrectly and will reduce the recognition rate of the single memristor crossbar architecture. These simulation results show that the single memristor crossbar architecture has more advantages compared with the complementary crossbar architecture when the images do have not many different densities, and none of the images have very low densities. This work also indicates that the single crossbar architecture must be improved by adding a constant term to deal with images that have low data densities. These are valuable case studies for archiving the advantages of single memristor crossbar architecture in neuromorphic computing applications. Full article

Equilibrium propagation (EP) has been proposed recently as a new neural network training algorithm based on a local learning concept, where only local information is used to calculate the weight update of the neural network. Despite the advantages of local learning, numerical iteration for solving the EP dynamic equations makes the EP algorithm less practical for realizing edge intelligence hardware. Some analog circuits have been suggested to solve the EP dynamic equations physically, not numerically, using the original EP algorithm. However, there are still a few problems in terms of circuit implementation: for example, the need for storing the free-phase solution and the lack of essential peripheral circuits for calculating and updating synaptic weights. Therefore, in this paper, a new analog circuit technique is proposed to realize the EP algorithm in practical and implementable hardware. This work has two major contributions in achieving this objective. First, the free-phase and nudge-phase solutions are calculated by the proposed analog circuits simultaneously, not at different times. With this process, analog voltage memories or digital memories with converting circuits between digital and analog domains for storing the free-phase solution temporarily can be eliminated in the proposed EP circuit. Second, a simple EP learning rule relying on a fixed amount of conductance change per programming pulse is newly proposed and implemented in peripheral circuits. The modified EP learning rule can make the weight update circuit practical and implementable without requiring the use of a complicated program verification scheme. The proposed memristor conductance update circuit is simulated and verified for training synaptic weights on memristor crossbars. The simulation results showed that the proposed EP circuit could be used for realizing on-device learning in edge intelligence hardware. Full article

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array. Full article

Memristive logic-in-memory circuits can provide energy- and cost-efficient computing, which is essential for artificial intelligence-based applications in the coming Internet-of-things era. Although memristive logic-in-memory circuits have been previously reported, the logic architecture requiring additional components and the non-uniform switching of memristor have restricted demonstrations to simple gates. Using a nanoscale graphene oxide (GO) nanosheets-based memristor, we demonstrate the feasibility of a non-volatile logic-in-memory circuit that enables normally-off in-memory computing. The memristor based on GO film with an abundance of unusual functional groups exhibited unipolar resistive switching behavior with reliable endurance and retention characteristics, making it suitable for logic-in-memory circuit application. In a state of low resistance, temperature-dependent resistance and I-V characteristics indicated the presence of a metallic Ni filament. Using memristor-aided logic (MAGIC) architecture, we performed NOT and NOR gates experimentally. Additionally, other logic gates such as AND, NAND, and OR were successfully implemented by combining NOT and NOR universal logic gates in a crossbar array. These findings will pave the way for the development of next-generation computer systems beyond the von Neumann architecture, as well as carbon-based nanoelectronics in the future. Full article

The design of memristor-based electronic circuits and devices gives researchers opportunities for the engineering of CMOS-memristor-based electronic integrated chips with ultra-high density and various applications. Metal-oxide memristors have good compatibility with the present CMOS integrated circuits technologies. The analysis of new electronic circuits requires suitable software and fast-functioning models. The main purpose of this paper is to propose the application of several modified, simplified, and improved metal-oxide memristor models in electronic devices and provide a comparison of their behavior, basic characteristics, and properties. According to this, LTSPICE is utilized in this paper because it is a free software product with good convergence. Several memristor-based electronic circuits, such as non-volatile passive and hybrid memory crossbars, a neural network, and different reconfigurable devices–filters, an amplifier, and a generator are analyzed in the LTSPICE environment, applying several standards and modified metal-oxide memristor models. After a comparison of the operation of the considered schemes, the main advantages of the modified metal-oxide memristor models, according to their standard analogs, are expressed, including fast operation, good accuracy, respectable convergence, switching properties, and successful applicability in complex electronic circuits. Full article

Memristor crossbars can be very useful for realizing edge-intelligence hardware, because the neural networks implemented by memristor crossbars can save significantly more computing energy and layout area than the conventional CMOS (complementary metal–oxide–semiconductor) digital circuits. One of the important operations used in neural networks is convolution. For performing the convolution by memristor crossbars, the full image should be partitioned into several sub-images. By doing so, each sub-image convolution can be mapped to small-size unit crossbars, of which the size should be defined as 128 × 128 or 256 × 256 to avoid the line resistance problem caused from large-size crossbars. In this paper, various convolution schemes with 3D, 2D, and 1D kernels are analyzed and compared in terms of neural network’s performance and overlapping overhead. The neural network’s simulation indicates that the 2D + 1D kernels can perform the sub-image convolution using a much smaller number of unit crossbars with less rate loss than the 3D kernels. When the CIFAR-10 dataset is tested, the mapping of sub-image convolution of 2D + 1D kernels to crossbars shows that the number of unit crossbars can be reduced almost by 90% and 95%, respectively, for 128 × 128 and 256 × 256 crossbars, compared with the 3D kernels. On the contrary, the rate loss of 2D + 1D kernels can be less than 2%. To improve the neural network’s performance more, the 2D + 1D kernels can be combined with 3D kernels in one neural network. When the normalized ratio of 2D + 1D layers is around 0.5, the neural network’s performance indicates very little rate loss compared to when the normalized ratio of 2D + 1D layers is zero. However, the number of unit crossbars for the normalized ratio = 0.5 can be reduced by half compared with that for the normalized ratio = 0. Full article

Irregular brain activity is of interest to researchers and scientists who are trying to understand, model, compare, and provide novel solutions to existing and challenging issues. Neurological disorders such as epilepsy, Alzheimer’s disease, Parkinson’s disease, and schizophrenia have been extensively studied. Among those diseases, epileptic seizures are the most commonly occurring ones. In this work, as a simplification of the complete biological operations of the brain, it was viewed as a system that consists of coupled oscillators. This allowed us to examine epilepsy as a pathological manifestation of the system. Emerging behaviors that arise from the spatiotemporal interactions of simple oscillators, namely, Chua’s Circuit, allowed us to observe how irregularities and changes to the coupling parameters of a neuromorphic network affect their synchronization and result in the emergence of epileptic activity. To achieve this, the characteristics of novel nanoelectronic devices, namely, memristors, have been exploited through their integration into two-dimensional crossbar arrays that offer the advantages of reprogrammability, low area, and low power consumption. Full article