VLSI-Based Sequential Devices in Cyber-Physical Systems

Dear Colleagues,

Cyber–physical systems (CPSs) are widely used in many fields of human activity. These systems significantly impact the quality of our lives. As a rule, CPSs can be viewed as a composition of microcontrollers (microprocessors) and various specific blocks. Various sequential devices (SDs) are crucial CPSs. They can be used as control units of a system, controllers of protocols, and can be responsible for the cooperation of a central processing unit with various accelerators. The quality of such SDs determines the quality of a particular CPS. Often, to represent the behavior of SDs, the models of Petri nets and FSM are used. Currently, microelectronics become nanoelectronics. For this reason, modern CPSs include application-specified integrated circuits (ASICs), application-specified standard products (ASSPs), and field-programmable gate arrays (FPGAs). A single chip is enough to implement a very complex cyber–physical system. This phenomenon has led to the need to develop new design methods taking into account the specifics of ASIC, ASSP, and FPGAs. As a result, designers of SDs face the following challenge: a sequential device circuit with the smallest possible hardware, propagation time, and energy consumed must be implemented. All these characteristics must be balanced. The ever-increasing complexity of modern and future CPSs requires the development of efficient computer-aided design tools to implement complex sequential devices. The aim of this Topic is to expand research on the practical and theoretical aspects associated with the design of sequential devices and the application of SD-based blocks in modern cyber–physical systems. The key focus is to present theoretical advances, as well as new design and verification methods to improve the quality of SD-based circuits as elements of modern cyber–physical systems. Topics may include, but are not limited, the following:

• Development of theory of sequential devices;
• Development of methods of state assignment targeting improving basic characteristics of sequential devices (chip area, performance, and consumed energy); 
• Improving the specification of SDs targeting real-scale projects; 
• Design of energy-efficient SDs; 
• Development of hardware-dependent design methods targeting SDs implemented with ASICs, ASSP and FPGAs; 
• Development of design methods for asynchronous SDs;
• Development of hardware-dependent and hardware-independent computer-aided design tools targeting SDs; 
• Development of design methods for hierarchical SDs; 
• Improving testability of complex SDs;
• Development of advanced methods of verification of SD-based circuits.

Prof. Dr. Alexander Barkalov
Prof. Dr. Larysa Titarenko
Dr. Kazimierz Krzywicki
Topic Editors