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Electronics
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Rapid System Design with Dedicated Architectures and Specific Software Tools
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Rapid System Design with Dedicated Architectures and Specific Software Tools

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (8 April 2016) | Viewed by 25128

Special Issue Editors

Prof. Dr. Gabriela Nicolescu

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Guest Editor
Ecole Polytechnique de Montréal, Montréal, QC, Canada
Interests: desing space exploration for emerging technologies HW/SW embedded system design; MPSoC
Prof. Dr. Frédéric Rousseau

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Guest Editor
TIMA – University of Grenoble-Alpes, Grenoble, France
Interests: low level software; HW/SW prototyping, MPSoC architecture
Prof. Dr. Amer Baghdadi

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Guest Editor
Lab-STICC, Telecom Bretagne, France
Interests: HW/SW embedded system design and prototyping; MPSoC; ASIP; NoC; flexible architecture design

Special Issue Information

Dear Colleagues,

System design has been under pressure for the last few decades due to increasing time constraints, even with the emergence of new design methodologies and tools. Therefore, there is still room for improvement, both in terms of (1) dedicated architectures that could be rapidly built and validated, and (2) specific software design tools that help in accelerating design. Dedicated architectures include new features in computing units or original application mapping based on multiprocessor and NoC architectures. Software design tools concern new system design optimizations in the design process or new design methodologies. Such research activities should lead to a more Rapid System Design process.

This Special Issue seeks original contributions on this research topic, encompassing a wide scope, ranging from MPSoC and GPU-based system design and validation for high performance computing, to hardware platforms and approaches for simulation acceleration. Potential topics include, but are not limited to:

  • Emerging technologies, devices and applications
  • Prototyping of embedded systems for real-time, low power and flexibility
  • Virtualization, prototyping and platforms
  • Formal methods and verification/validation
  • Reliability and failure analysis
  • Safety and design of critical systems
  • Methods and tools for reconfigurable computing
  • MPSoC and GPU-based system design and challenges
  • Rapid design approaches for application-specific processors

Prof. Dr. Gabriela Nicolescu
Prof. Dr. Frédéric Rousseau
Prof. Dr. Amer Baghdadi
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (4 papers)

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38452 KiB  
Article
ROSMOD: A Toolsuite for Modeling, Generating, Deploying, and Managing Distributed Real-time Component-based Software using ROS
by Pranav Srinivas Kumar, William Emfinger, Gabor Karsai, Dexter Watkins, Benjamin Gasser and Amrutur Anilkumar
Electronics 2016, 5(3), 53; https://doi.org/10.3390/electronics5030053 - 07 Sep 2016
Cited by 6 | Viewed by 8243
Abstract
This paper presents the Robot Operating System Model-driven development tool suite, (ROSMOD) an integrated development environment for rapid prototyping component-based software for the Robot Operating System (ROS) middleware. ROSMOD is well suited for the design, development and deployment of large-scale distributed applications on [...] Read more.
This paper presents the Robot Operating System Model-driven development tool suite, (ROSMOD) an integrated development environment for rapid prototyping component-based software for the Robot Operating System (ROS) middleware. ROSMOD is well suited for the design, development and deployment of large-scale distributed applications on embedded devices. We present the various features of ROSMOD including the modeling language, the graphical user interface, code generators, and deployment infrastructure. We demonstrate the utility of this tool with a real-world case study: an Autonomous Ground Support Equipment (AGSE) robot that was designed and prototyped using ROSMOD for the NASA Student Launch competition, 2014–2015. Full article
(This article belongs to the Special Issue Rapid System Design with Dedicated Architectures and Specific Software Tools)
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4693 KiB  
Article
Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping
by Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna and Youssef Atat
Electronics 2016, 5(3), 50; https://doi.org/10.3390/electronics5030050 - 30 Aug 2016
Cited by 9 | Viewed by 6302
Abstract
In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the [...] Read more.
In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC) approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTL)synthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations. Full article
(This article belongs to the Special Issue Rapid System Design with Dedicated Architectures and Specific Software Tools)
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872 KiB  
Article
Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study
by Denis Becker, Matthieu Moy and Jérôme Cornet
Electronics 2016, 5(2), 22; https://doi.org/10.3390/electronics5020022 - 17 May 2016
Cited by 3 | Viewed by 5224
Abstract
Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential [...] Read more.
Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level. Full article
(This article belongs to the Special Issue Rapid System Design with Dedicated Architectures and Specific Software Tools)
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6899 KiB  
Article
A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis
by Shirish Bahirat and Sudeep Pasricha
Electronics 2016, 5(2), 21; https://doi.org/10.3390/electronics5020021 - 14 May 2016
Cited by 5 | Viewed by 4763
Abstract
Network on Chip (NoC) architectures have emerged in recent years as scalable communication fabrics to enable high bandwidth data transfers in chip multiprocessors (CMPs). These interconnection architectures still need to conquer many challenges, e.g., significant power consumption and high data transfer latencies. Hybrid [...] Read more.
Network on Chip (NoC) architectures have emerged in recent years as scalable communication fabrics to enable high bandwidth data transfers in chip multiprocessors (CMPs). These interconnection architectures still need to conquer many challenges, e.g., significant power consumption and high data transfer latencies. Hybrid electro-photonic NoCs have been recently proposed as a solution to mitigate some of these challenges. However, with increasing application complexity, hardware dependencies, and performance variability, optimization of hybrid photonic NoCs requires traversing a massive design space. To date, prior work on software tools for rapid automated NoC synthesis have mainly focused on electrical NoCs. In this article, we propose a novel suite of software tools for effectively synthesizing hybrid photonic NoCs. We formulate and solve the synthesis problem using four search-based optimization heuristics: (1) Ant Colony Optimization (ACO); (2) Particle Swarm Optimization (PSO); (3) Genetic Algorithm (GA); and (4) Simulated Annealing (SA). Our experimental results show significant promise for the ACO and PSO based heuristics. Our novel implementation of PSO achieves an average of 64% energy-delay product improvements over GA and 53% improvement over SA; while our novel ACO implementation achieves 107% energy-delay product improvements over GA and 62% improvement over SA. Full article
(This article belongs to the Special Issue Rapid System Design with Dedicated Architectures and Specific Software Tools)
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