Journal Description
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications
is an international, peer-reviewed, open access journal on low power electronics published quarterly online by MDPI.
- Open Access— free for readers, with article processing charges (APC) paid by authors or their institutions.
- High Visibility: indexed within Scopus, ESCI (Web of Science), Inspec, and other databases.
- Rapid Publication: manuscripts are peer-reviewed and a first decision is provided to authors approximately 23.2 days after submission; acceptance to publication is undertaken in 4.6 days (median values for papers published in this journal in the first half of 2024).
- Journal Rank: CiteScore - Q2 (Electrical and Electronic Engineering)
- Recognition of Reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
Impact Factor:
1.6 (2023)
Latest Articles
Energy Restoration in Data Drivers for Low-Power Digitally Driven OLEDoS Microdisplays
J. Low Power Electron. Appl. 2024, 14(4), 48; https://doi.org/10.3390/jlpea14040048 - 4 Oct 2024
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Microdisplays are widely used in near-to-eye (NTE) applications that operate with batteries, and reducing the power consumption of microdisplays is key to increasing their battery life. This paper proposes a digital data driver with a data energy recycling feature to reduce its dynamic
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Microdisplays are widely used in near-to-eye (NTE) applications that operate with batteries, and reducing the power consumption of microdisplays is key to increasing their battery life. This paper proposes a digital data driver with a data energy recycling feature to reduce its dynamic power consumption. According to the measurement results obtained from a proof-of-concept array fabricated using TSMC 65 nm technology, the power consumption of the display data driver demonstrates an average reduction of 16% when tested with 10 random black-and-white images or a 14.4% decrease when evaluated using four real-life test images.
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Open AccessArticle
Reliability Enhancement Methods for Relaxation Oscillator with Delay Time Cancellation
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Kunpeng Xu, Hongguang Dai, Zhanxia Wu, Zhibo Huang, Guoqiang Zhang, Xiaopeng Yu, Wechang Wang and Gang Xuan
J. Low Power Electron. Appl. 2024, 14(4), 47; https://doi.org/10.3390/jlpea14040047 - 26 Sep 2024
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Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the
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Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the low-power delay time cancellation (DTC) technique and several enhancement methods, including a novel offset trimming approach, an error state detection and recovery (ESDAR) circuit, and a specialized frequency-trimming method. Simulation results for an 8 MHz relaxation oscillator in a 40 nm CMOS process show that the proposed DTC technique and enhancements improve frequency variation due to power supply fluctuations to ±0.05% and reduce temperature-induced frequency variation to ±0.4%.
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Open AccessArticle
IoT-MFaceNet: Internet-of-Things-Based Face Recognition Using MobileNetV2 and FaceNet Deep-Learning Implementations on a Raspberry Pi-400
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Ahmad Saeed Mohammad, Thoalfeqar G. Jarullah, Musab T. S. Al-Kaltakchi, Jabir Alshehabi Al-Ani and Somdip Dey
J. Low Power Electron. Appl. 2024, 14(3), 46; https://doi.org/10.3390/jlpea14030046 - 5 Sep 2024
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IoT applications revolutionize industries by enhancing operations, enabling data-driven decisions, and fostering innovation. This study explores the growing potential of IoT-based facial recognition for mobile devices, a technology rapidly advancing within the interconnected IoT landscape. The investigation proposes a framework called IoT-MFaceNet (Internet-of-Things-based
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IoT applications revolutionize industries by enhancing operations, enabling data-driven decisions, and fostering innovation. This study explores the growing potential of IoT-based facial recognition for mobile devices, a technology rapidly advancing within the interconnected IoT landscape. The investigation proposes a framework called IoT-MFaceNet (Internet-of-Things-based face recognition using MobileNetV2 and FaceNet deep-learning) utilizing pre-existing deep-learning methods, employing the MobileNetV2 and FaceNet algorithms on both ImageNet and FaceNet databases. Additionally, an in-house database is compiled, capturing data from 50 individuals via a web camera and 10 subjects through a smartphone camera. Pre-processing of the in-house database involves face detection using OpenCV’s Haar Cascade, Dlib’s CNN Face Detector, and Mediapipe’s Face. The resulting system demonstrates high accuracy in real-time and operates efficiently on low-powered devices like the Raspberry Pi 400. The evaluation involves the use of the multilayer perceptron (MLP) and support vector machine (SVM) classifiers. The system primarily functions as a closed set identification system within a computer engineering department at the College of Engineering, Mustansiriyah University, Iraq, allowing access exclusively to department staff for the department rapporteur room. The proposed system undergoes successful testing, achieving a maximum accuracy rate of 99.976%.
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Open AccessArticle
Split-Voltage Configuration Improves Integrated Amplifier Power-Efficiency
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Sebastian Simmich and Robert Rieger
J. Low Power Electron. Appl. 2024, 14(3), 45; https://doi.org/10.3390/jlpea14030045 - 4 Sep 2024
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A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V
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A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application.
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Open AccessArticle
Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration
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Baudouin Chauviere and Kenneth S. Stevens
J. Low Power Electron. Appl. 2024, 14(3), 44; https://doi.org/10.3390/jlpea14030044 - 27 Aug 2024
Abstract
Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the
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Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing.
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(This article belongs to the Special Issue Energy Aware Scientific Computing in Distributed Architectures, Low Power Processors and HPC Hybrid Systems)
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Prospective Review of Magneto-Resistive Current Sensors with High Sensitivity and Wide Temperature Range
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Zicai Yang and Yanfeng Jiang
J. Low Power Electron. Appl. 2024, 14(3), 43; https://doi.org/10.3390/jlpea14030043 - 19 Aug 2024
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Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research
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Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research process of the current sensors in industrial-level applications. In the review, starting with the development status of the current sensors, the physical mechanisms of the relevant magneto-resistive effects and their early applications as the current sensors are introduced. Several design methods of the magnetic sensors, as well as their merits and shortcomings, are summarized. The performance parameters of the magnetic sensors based on AMR, GMR, TMR and Hall effects are reviewed, including the front-end amplification circuits and conditioning circuits. The industrial applications of the current sensors in the fields of automobiles and photovoltaic inverters are enumerated. The criterions for the current sensors to be used in different scenarios are discussed. In the future, it is imperative to continue the research and development of novel current sensors in order to satisfy the increasingly stringent demands of the industrial developments, in terms of the performance, cost and reliability of the current sensors.
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Open AccessArticle
Field-Programmable Gate Array Architecture for the Discrete Orthonormal Stockwell Transform (DOST) Hardware Implementation
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Martin Valtierra-Rodriguez, Jose-Luis Contreras-Hernandez, David Granados-Lieberman, Jesus Rooney Rivera-Guillen, Juan Pablo Amezquita-Sanchez and David Camarena-Martinez
J. Low Power Electron. Appl. 2024, 14(3), 42; https://doi.org/10.3390/jlpea14030042 - 7 Aug 2024
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Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern
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Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern recognition. Recently, the Discrete Orthonormal Stockwell Transform (DOST) has become increasingly utilized in many specialized signal processing tasks. Given its growing importance, this work proposes a reconfigurable field-programmable gate array (FPGA) architecture designed to efficiently implement the DOST algorithm on cost-effective FPGA chips. An accompanying MATLAB app enables the automatic configuration of the DOST method for varying sizes (64, 128, 256, 512, and 1024 points). For the implementation, a Cyclone V series FPGA device from Intel Altera, featuring the 5CSEMA5F31C6N chip, is used. To provide a complete hardware solution, the proposed DOST core has been integrated into a hybrid ARM-HPS (Advanced RISC Machine–Hard Processor System) control unit, which allows the control of different peripherals, such as communication protocols and VGA-based displays. Results show that less than 5% of the chip’s resources are occupied, indicating a low-cost architecture that can be easily integrated into other FPGA structures or hardware systems for diverse applications. Moreover, the accuracy of the proposed FPGA-based implementation is underscored by a root mean squared error of 6.0155 × 10−3 when compared with results from floating-point processors, highlighting its accuracy.
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Open AccessArticle
A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses
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Benjamin Villegas and Ioannis Vourkas
J. Low Power Electron. Appl. 2024, 14(3), 41; https://doi.org/10.3390/jlpea14030041 - 5 Aug 2024
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Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a
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Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells.
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Open AccessArticle
A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing
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Ali Namdari, Orazio Aiello and Daniele D. Caviglia
J. Low Power Electron. Appl. 2024, 14(3), 40; https://doi.org/10.3390/jlpea14030040 - 4 Aug 2024
Abstract
A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in
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A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier
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Riccardo Della Sala, Francesco Centurelli and Giuseppe Scotti
J. Low Power Electron. Appl. 2024, 14(3), 39; https://doi.org/10.3390/jlpea14030039 - 24 Jul 2024
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An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to
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An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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A 0.064 mm2 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach
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Giovanni Nicolini, Alessandro Fava, Francesco Centurelli and Giuseppe Scotti
J. Low Power Electron. Appl. 2024, 14(3), 38; https://doi.org/10.3390/jlpea14030038 - 13 Jul 2024
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In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio
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In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 m × 65 m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 . Power consumption is also tested, with a measured value of 3.77 W per channel, corresponding to an overall consumption of about 60 W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording
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Xuan Phuong Tran, Xuan Thuc Kieu, Xuan Thanh Pham, Duy Phong Pham and Manh Kha Hoang
J. Low Power Electron. Appl. 2024, 14(3), 37; https://doi.org/10.3390/jlpea14030037 - 10 Jul 2024
Abstract
Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input
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Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Zin) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Zin of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm2 CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µVrms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor
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Muhammad Omer Shah, Manfredi Caruso and Salvatore Pennisi
J. Low Power Electron. Appl. 2024, 14(3), 36; https://doi.org/10.3390/jlpea14030036 - 7 Jul 2024
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This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was
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This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Spin–Orbit Coupling Free Nonlinear Spin Hall Effect in a Triangle-Unit Collinear Antiferromagnet with Magnetic Toroidal Dipole
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Satoru Hayami
J. Low Power Electron. Appl. 2024, 14(3), 35; https://doi.org/10.3390/jlpea14030035 - 3 Jul 2024
Abstract
We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear
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We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear spin conductivity has Hall-type characterization. We demonstrate the emergence of both spin conductivities in a breathing kagome system consisting of a triangle cluster. The nonlinear spin conductivity becomes larger than the linear one when the Fermi level lies near the region where a small partial band gap opens. Our results indicate that collinear antiferromagnets with triangular geometry give rise to rich spin conductive phenomena.
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(This article belongs to the Special Issue Recent Advances in Spintronics)
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Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic
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William Morell and Jin-Woo Choi
J. Low Power Electron. Appl. 2024, 14(3), 34; https://doi.org/10.3390/jlpea14030034 - 27 Jun 2024
Abstract
Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often
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Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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OptimalNN: A Neural Network Architecture to Monitor Chemical Contamination in Cancer Alley
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Uchechukwu Leo Udeji and Martin Margala
J. Low Power Electron. Appl. 2024, 14(2), 33; https://doi.org/10.3390/jlpea14020033 - 10 Jun 2024
Abstract
The detrimental impact of toxic chemicals, gas, and oil spills in aquatic environments poses a severe threat to plants, animals, and human life. Regions such as Cancer Alley exemplify the profound consequences of inadequately controlled chemical spills, significantly affecting the local community. Given
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The detrimental impact of toxic chemicals, gas, and oil spills in aquatic environments poses a severe threat to plants, animals, and human life. Regions such as Cancer Alley exemplify the profound consequences of inadequately controlled chemical spills, significantly affecting the local community. Given the far-reaching effects of these spills, it has become imperative to devise an efficient method for early monitoring, estimation, and cleanup, utilizing affordable and effective techniques. In this research, we explore the application of U-shaped neural Network (UNET) and U-shaped neural network transformer (UNETR) neural network models designed for the image segmentation of chemical and oil spills. Our models undergo training using the Commonwealth Scientific and Industrial Research Organization (CSIRO) dataset and the Oil Spill Detection dataset, employing a specialized filtering technique to enhance detection accuracy. We achieved training accuracies of 95.35% and 91% by applying UNET on the Oil Spill and the CSIRO datasets after 50 epochs of training, respectively. We also achieved a training accuracy of 75% by applying UNETR to the Oil Spill dataset. Additionally, we integrated mixed precision to expedite the model training process, thus maximizing data throughput. To further accelerate our implementation, we propose the utilization of the Field Programmable Gate Array (FPGA) architecture. The results obtained from our study demonstrate improvements in inference latency on FPGA.
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(This article belongs to the Special Issue Advancements in Low-Power Ubiquitous Sensing, Computing, and Communication Interfaces for IoT: Circuits, Systems, and Applications)
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A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor
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Xinyuan He, Weifeng Qiao, Xinpeng Xing and Haigang Feng
J. Low Power Electron. Appl. 2024, 14(2), 32; https://doi.org/10.3390/jlpea14020032 - 4 Jun 2024
Abstract
A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier
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A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.
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(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)
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Modeling Excitable Cells with Memristors
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Maheshwar Sah, Alon Ascoli, Ronald Tetzlaff, Vetriveeran Rajamani and Ram Kaji Budhathoki
J. Low Power Electron. Appl. 2024, 14(2), 31; https://doi.org/10.3390/jlpea14020031 - 28 May 2024
Cited by 1
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This paper presents an in-depth analysis of an excitable membrane of a biological system by proposing a novel approach that the cells of the excitable membrane can be modeled as the networks of memristors. We provide compelling evidence from the Chay neuron model
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This paper presents an in-depth analysis of an excitable membrane of a biological system by proposing a novel approach that the cells of the excitable membrane can be modeled as the networks of memristors. We provide compelling evidence from the Chay neuron model that the state-independent mixed ion channel is a nonlinear resistor, while the state-dependent voltage-sensitive potassium ion channel and calcium-sensitive potassium ion channel function as generic memristors from the perspective of electrical circuit theory. The mechanisms that give rise to periodic oscillation, aperiodic (chaotic) oscillation, spikes, and bursting in an excitable cell are also analyzed via a small-signal model, a pole-zero diagram of admittance functions, local activity, the edge of chaos, and the Hopf bifurcation theorem. It is also proved that the zeros of the admittance functions are equivalent to the eigen values of the Jacobian matrix, and the presence of the positive real parts of the eigen values between the two bifurcation points lead to the generation of complicated electrical signals in an excitable membrane. The innovative concepts outlined in this paper pave the way for a deeper understanding of the dynamic behavior of excitable cells, offering potent tools for simulating and exploring the fundamental characteristics of biological neurons.
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Open AccessArticle
A Simple, Robust, and Versatile MATLAB Formulation of the Dynamic Memdiode Model for Bipolar-Type Resistive Random Access Memory Devices
by
Emili Salvador, Rosana Rodriguez and Enrique Miranda
J. Low Power Electron. Appl. 2024, 14(2), 30; https://doi.org/10.3390/jlpea14020030 - 28 May 2024
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Modeling in an emerging technology like RRAM devices is one of the pivotal concerns for its development. In the current bibliography, most of the models face difficulties in implementing or simulating unconventional scenarios, particularly when dealing with complex input signals. In addition, circuit
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Modeling in an emerging technology like RRAM devices is one of the pivotal concerns for its development. In the current bibliography, most of the models face difficulties in implementing or simulating unconventional scenarios, particularly when dealing with complex input signals. In addition, circuit simulators like Spice require long running times for high-resolution results because of their internal mathematical implementation. In this work, a fast, simple, robust, and versatile model for RRAM devices built in MATLAB is presented. The proposed model is a recursive and discretized version of the dynamic memdiode model (DMM) for bipolar-type resistive switching devices originally implemented in LTspice. The DMM model basically consists of two coupled equations: one for the current (non-linear current generator) and a second one for the memory state of the device (time-dependent differential equation). This work presents an easy-to-use tool for researchers to reproduce the experimental behavior of their devices and predict the outcome from non-trivial experiments. Three study cases are reported, aimed at capturing different phenomenologies: a frequency effect study, a cycle-to-cycle variability fit, and a stochastic resonance impact analysis.
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Open AccessArticle
Coordination of SRF-PLL and Grid Forming Inverter Control in Microgrid with Solar PV and Energy Storage
by
V. Vignesh Babu, J. Preetha Roselyn and Prabha Sundaravadivel
J. Low Power Electron. Appl. 2024, 14(2), 29; https://doi.org/10.3390/jlpea14020029 - 21 May 2024
Cited by 1
Abstract
Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators,
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Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid’s reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system.
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(This article belongs to the Special Issue Energy Aware Solutions for Battery Management Systems)
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