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4 pages, 152 KiB

Open AccessEditorial

Advanced CMOS Devices and Applications

by Choonghyun Lee and Yi Zhao

Electronics 2024, 13(1), 134; https://doi.org/10.3390/electronics13010134 - 28 Dec 2023

Viewed by 1278

Abstract

The persistent scaling of transistor dimensions has marked an era characterized by a fourfold increase in transistor density and a twofold boost in electrical performance every 2–3 years, effectively reducing their cost per function [...] Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

Research

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11 pages, 2541 KiB

Open AccessCommunication

Ti/HfO₂-Based RRAM with Superior Thermal Stability Based on Self-Limited TiO_x

by Huikai He, Yixin Tan, Choonghyun Lee and Yi Zhao

Electronics 2023, 12(11), 2426; https://doi.org/10.3390/electronics12112426 - 26 May 2023

Cited by 4 | Viewed by 2560

Abstract

HfO₂-based resistive random-access memory (RRAM) with a Ti buffer layer has been extensively studied as an emerging nonvolatile memory (eNVM) candidate because of its excellent resistive switching (RS) properties and CMOS process compatibility. However, a detailed understanding of the nature of [...] Read more.

HfO₂-based resistive random-access memory (RRAM) with a Ti buffer layer has been extensively studied as an emerging nonvolatile memory (eNVM) candidate because of its excellent resistive switching (RS) properties and CMOS process compatibility. However, a detailed understanding of the nature of Ti thickness-dependent RS and systematic thermal degradation research about the effect of post-metallization annealing (PMA) time on oxygen vacancy distribution and RS performance still needs to be included. Herein, the impact of Ti buffer layer thickness on the RS performance of the Al/Ti/HfO₂/TiN devices is first addressed. Consequently, we have proposed a simple strategy to regulate the leakage current, forming voltage, memory window, and uniformity by varying the thickness of the Ti layer. Moreover, it is found that the device with 15 nm Ti shows the minimum cycle-to-cycle variability (CCV) and device-to-device variability (DDV), good retention (10⁵ s at 85 °C), and superior endurance (10⁴). In addition, thermal degradation of the Al/Ti(15 nm)/HfO₂/TiN devices under different PMA times at 400 °C is carried out. It is found that the leakage current increases and the forming voltage and memory window decrease with the increase in PMA time due to the thermally activated oxidation of the Ti. However, when the PMA time increases to 30 min, the Ti can no longer capture oxygen from HfO₂ due to the formation of self-limited TiO_x. Therefore, the device shows superior thermal stability with a PMA time of 90 min at 400 °C and no degradation of the memory window, uniformity, endurance, or retention. This work demonstrates that the Ti/HfO₂-based RRAM shows superior back-end-of-line compatibility with high thermal stability up to 400 °C for over an hour. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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9 pages, 3591 KiB

Open AccessCommunication

HfO_x/Ge RRAM with High ON/OFF Ratio and Good Endurance

by Na Wei, Xiang Ding, Shifan Gao, Wenhao Wu and Yi Zhao

Electronics 2022, 11(22), 3820; https://doi.org/10.3390/electronics11223820 - 20 Nov 2022

Cited by 2 | Viewed by 2523

Abstract

A trade-off between the memory window and the endurance exists for transition-metal-oxide RRAM. In this work, we demonstrated that HfO_x/Ge-based metal-insulator-semiconductor RRAM devices possess both a larger memory window and longer endurance compared with metal-insulator-metal (MIM) RRAM devices. Under DC cycling, [...] Read more.

A trade-off between the memory window and the endurance exists for transition-metal-oxide RRAM. In this work, we demonstrated that HfO_x/Ge-based metal-insulator-semiconductor RRAM devices possess both a larger memory window and longer endurance compared with metal-insulator-metal (MIM) RRAM devices. Under DC cycling, HfO_x/Ge devices exhibit a 100× larger memory window compared to HfO_x MIM devices, and a DC sweep of up to 20,000 cycles was achieved with the devices. The devices also realize low static power down to 1 nW as FPGA’s pull-up/pull-down resistors. Thus, HfO_x/Ge devices act as a promising candidates for various applications such as FPGA or compute-in-memory, in which both a high ON/OFF ratio and decent endurance are required. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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11 pages, 483 KiB

Open AccessArticle

A Review of the Gate-All-Around Nanosheet FET Process Opportunities

by Sagarika Mukesh and Jingyun Zhang

Electronics 2022, 11(21), 3589; https://doi.org/10.3390/electronics11213589 - 3 Nov 2022

Cited by 31 | Viewed by 30802

Abstract

In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges [...] Read more.

In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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12 pages, 6293 KiB

Open AccessArticle

Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon

by Geon Uk Kim, Young Jun Yoon, Jae Hwa Seo, Sang Ho Lee, Jin Park, Ga Eon Kang, Jun Hyeok Heo, Jaewon Jang, Jin-Hyuk Bae, Sin-Hyung Lee and In Man Kang

Electronics 2022, 11(20), 3365; https://doi.org/10.3390/electronics11203365 - 18 Oct 2022

Cited by 3 | Viewed by 3053

Abstract

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers [...] Read more.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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15 pages, 1534 KiB

Open AccessArticle

Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors

by SangMin Woo, HyunJoon Jeong, JinYoung Choi, HyungMin Cho, Jeong-Taek Kong and SoYoung Kim

Electronics 2022, 11(17), 2761; https://doi.org/10.3390/electronics11172761 - 1 Sep 2022

Cited by 12 | Viewed by 5538

Abstract

In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD [...] Read more.

In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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9 pages, 2678 KiB

Open AccessArticle

Independent Effects of Dopant, Oxygen Vacancy, and Specific Surface Area on Crystal Phase of HfO₂ Thin Films towards General Parameters to Engineer the Ferroelectricity

by Tianning Cui, Liping Zhu, Danyang Chen, Yuyan Fan, Jingquan Liu and Xiuyan Li

Electronics 2022, 11(15), 2369; https://doi.org/10.3390/electronics11152369 - 28 Jul 2022

Cited by 2 | Viewed by 2659

Abstract

Many factors have been confirmed to affect ferroelectric phase formation in HfO₂-based thin films but there was still a lack of general view on describing them. This paper discusses the intrinsic parameters to stabilize the ferroelectric phase of HfO₂ thin [...] Read more.

Many factors have been confirmed to affect ferroelectric phase formation in HfO₂-based thin films but there was still a lack of general view on describing them. This paper discusses the intrinsic parameters to stabilize the ferroelectric phase of HfO₂ thin films to approach this general view by investigating the separate effects of dopant, oxygen vacancy (V_O), and specific surface area on the crystal phase of the films. It is found that in addition to extensively studied dopants, the ferroelectric orthorhombic phase can also be formed in pure HfO₂ films by only introducing sufficient V_O independently, and it is also formable by only increasing the specific surface area. By analyzing the common physics behind these factors, it is found that orthorhombic phase formation is universally related to strain in all the above cases with a given temperature. To get a general view, a physical model is established to describe how the strain influences ferroelectric phase formation during the fabrication of HfO₂-based films based on thermodynamic and kinetics analysis. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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9 pages, 2303 KiB

Open AccessArticle

Simulation Study of Low Turn-Off Loss and Snapback-Free SA-IGBT with Injection-Enhanced p-Floating Layer

by Xiaodong Zhang, Ming Gong, Junfeng Pan, Mingxin Song, Hang Zhang and Linlin Zhang

Electronics 2022, 11(15), 2351; https://doi.org/10.3390/electronics11152351 - 28 Jul 2022

Cited by 1 | Viewed by 1655

Abstract

In this study, a shorted-anode IGBT with an injection-enhanced p-floating layer (IEPF-IGBT) under the N-buffer layer is proposed. Compared to conventional shorted-anode IGBT (SA-IGBT), the IEPF-IGBT has the structural characteristics of an injection-enhanced P-floating (IEPF) layer inserted into the N-buffer layer and [...] Read more.

In this study, a shorted-anode IGBT with an injection-enhanced p-floating layer (IEPF-IGBT) under the N-buffer layer is proposed. Compared to conventional shorted-anode IGBT (SA-IGBT), the IEPF-IGBT has the structural characteristics of an injection-enhanced P-floating (IEPF) layer inserted into the N-buffer layer and the P+ collector region. The IEPF layer and P+ collector region pinch off the electron path during the turn-on period to suppress the snapback effect with a half-cell pitch of 10 μm. In addition, the IEPF layer acts as an injection-enhanced layer that influences the current injection of the holes. There is 56.3% reduction in the turn-off loss of the IEPF-IGBT at the same forward voltage drop. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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12 pages, 3715 KiB

Open AccessArticle

A Novel Structure to Improve the Erase Speed in 3D NAND Flash Memory to Which a Cell-On-Peri (COP) Structure and a Ferroelectric Memory Device Are Applied

by Seonjun Choi, Jae Kyeong Jeong, Myounggon Kang and Yun-heub Song

Electronics 2022, 11(13), 2038; https://doi.org/10.3390/electronics11132038 - 29 Jun 2022

Cited by 1 | Viewed by 4662

Abstract

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through [...] Read more.

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through a pillar in the P+ crystal silicon sub-region located at the bottom of the 3D NAND flash structure to which the COP structure is applied. To verify this, we first confirmed that when the Gate Induced Drain Leakage (GIDL) erasing method used in the 3D NAND structure using the existing Charge Trap Flash (CTF) memory is applied as it is, the operation speed takes more than 10ms, for various reasons. Next, as a result of using the SP structure to solve this problem, even if the conventional erasing method was used until the thickness of the pillar was 20 nm, thanks to the rapidly supplied hole carriers, a fast-erasing rate of 1us was achieved. Additionally, this result is up to 10,000 times faster than the GIDL deletion method. Next, it was confirmed that when the pillar thickness is 10 nm, the erase operation time is greatly delayed by the conventional erasing method, but this can also be solved by appropriately adjusting the operating voltage and time. In conclusion, it was confirmed that, when the proposed SP structure is applied, it is possible to maximize the fast operation performance of the ferroelectric memory while securing the biggest advantage of the 3D NAND flash structure, the degree of integration. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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Review

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19 pages, 7325 KiB

Open AccessReview

Recent Research for HZO-Based Ferroelectric Memory towards In-Memory Computing Applications

by Jaewook Yoo, Hyeonjun Song, Hongseung Lee, Seongbin Lim, Soyeon Kim, Keun Heo and Hagyoul Bae

Electronics 2023, 12(10), 2297; https://doi.org/10.3390/electronics12102297 - 19 May 2023

Cited by 11 | Viewed by 8923

Abstract

The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash [...] Read more.

The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash memory systems, the large voltage required to erase the charge of nonvolatile memory cells, and the limitations of scaled-down systems. Ferroelectric materials are one exciting means of breaking away from this structure, as Hf-based ferroelectric materials have a low operating voltage, excellent data retention qualities, and show fast switching speed, and can be used as non-volatile memory (NVM) if polarization characteristics are utilized. Moreover, adjusting their conductance enables diverse computing architectures, such as neuromorphic computing with analog characteristics or ‘logic-in-memory’ computing with digital characteristics, through high integration. Several types of ferroelectric memories, including two-terminal-based FTJs, three-terminal-based FeFETs using electric field effect, and FeRAMs using ferroelectric materials as capacitors, are currently being studied. In this review paper, we include these devices, as well as a Fe-diode with high on/off ratio properties, which has a similar structure to the FTJs but operate with the Schottky barrier modulation. After reviewing the operating principles and features of each structure, we conclude with a summary of recent applications that have incorporated them. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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16 pages, 5366 KiB

Open AccessReview

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

by Jaeyong Jeong, Dae-Myeong Geum and SangHyeon Kim

Electronics 2022, 11(19), 3013; https://doi.org/10.3390/electronics11193013 - 22 Sep 2022

Cited by 14 | Viewed by 7368

Abstract

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important [...] Read more.

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (f_T) and unity power gain cutoff frequency (f_MAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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19 pages, 3520 KiB

Open AccessReview

Recent Trends in Copper Metallization

by Hyung-Woo Kim

Electronics 2022, 11(18), 2914; https://doi.org/10.3390/electronics11182914 - 14 Sep 2022

Cited by 19 | Viewed by 12687

Abstract

The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO₂ interconnects, but now that the technology generation has reached 1× nm or lower, a number of limitations have become apparent. Due to the integration limit of [...] Read more.

The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay of Al/SiO₂ interconnects, but now that the technology generation has reached 1× nm or lower, a number of limitations have become apparent. Due to the integration limit of low-k materials, the increase in the RC delay due to scaling can only be suppressed through metallization. As a result, various metallization methods have been proposed, including traditional barrier/liner thickness scaling, and new materials and integration schemes have been developed. This paper introduces these methods and summarizes the recent trends in metallization. It also includes a brief introduction to the Cu damascene process, an explanation of why the low-k approach faces limitations, and a discussion of the measures of reliability (electromigration and time-dependent dielectric breakdown) that are essential for all validation schemes. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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25 pages, 6893 KiB

Open AccessReview

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

by Toshiyuki Tabata, Fabien Rozé, Louis Thuries, Sébastien Halty, Pierre-Edouard Raynal, Imen Karmous and Karim Huet

Electronics 2022, 11(17), 2636; https://doi.org/10.3390/electronics11172636 - 23 Aug 2022

Cited by 2 | Viewed by 3814

Abstract

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material [...] Read more.

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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21 pages, 3877 KiB

Open AccessReview

Understanding and Controlling Band Alignment at the Metal/Germanium Interface for Future Electric Devices

by Tomonori Nishimura

Electronics 2022, 11(15), 2419; https://doi.org/10.3390/electronics11152419 - 3 Aug 2022

Cited by 9 | Viewed by 4087

Abstract

Germanium (Ge) is a promising semiconductor as an alternative channel material to enhance performance in scaled silicon (Si) field-effect transistor (FET) devices. The gate stack of Ge FETs has been much improved based on extensive research thus far, demonstrating that the performance of [...] Read more.

Germanium (Ge) is a promising semiconductor as an alternative channel material to enhance performance in scaled silicon (Si) field-effect transistor (FET) devices. The gate stack of Ge FETs has been much improved based on extensive research thus far, demonstrating that the performance of Ge FETs is much superior to that of Si FETs in terms of the on-state current. However, to suppress the performance degradation due to parasitic contact resistance at the metal/Ge interface in advanced nodes, the reduction of the Schottky barrier height (SBH) at the metal/Ge interface is indispensable, yet the SBH at the common metal/Ge interface is difficult to control by the work function of metal due to strong Fermi level pinning (FLP) close to the valence band edge of Ge. However, the strong FLP could be alleviated by an ultrathin interface layer or a low free-electron-density metal, which makes it possible to lower the SBH for the conduction band edge of Ge to less than 0.3 eV. The FLP alleviation is reasonably understandable by weakening the intrinsic metal-induced gap states at the metal/Ge interface and might be a key solution for designing scaled Ge n-FETs. Full article

(This article belongs to the Special Issue Advanced CMOS Devices and Applications)

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