Search Results (65)

This paper introduces a 0.5–5.8 GHz low-noise amplifier (LNA) incorporating a gyrator-C-based active inductor (AI) and an enhanced deep trench isolation (DTI) electrostatic discharge (ESD) diode. Results suggest that AIs exhibit excellent consistency under various process voltage temperatures (PVTs) as well as input powers and the improved DTI diodes reduce parasitic capacitance by an average of 8.5% compared to conventional ones. In terms of circuit design, comprehensive analyses of gain flatness and noise are conducted. Fabricated using a 0.18 μm SiGe BiCMOS technology, the LNA delivers a high S21 of 18.3 ± 0.3 dB, a minimum noise figure of 2.6 dB, and an S11 and S22 of less than −10 dB over the entire frequency band. Operating from a 3.3 V supply voltage with a core area of 0.049 mm², it consumes 10 mA of current. Full article

This paper presents a wideband low-power/low-voltage 60-GHz low-noise amplifier (LNA) in a 28-nm bulk CMOS technology. The LNA has been designed for high-speed millimeter-wave (mm-wave) communications. It consists of two pseudo-differential amplifying stages and a buffer stage included for 50-Ohm on-wafer measurements. Two integrated input/output baluns guarantee both simultaneous 50-ohm input–noise/output matching at input/output radio frequency (RF) pads. A power-efficient design strategy is adopted to make the LNA suitable for low-power applications, while minimizing the noise figure (NF). Thanks to the adopted design strategy, the post-layout simulation results show an excellent trade-off between power gain and 3-dB bandwidth (BW_3dB) with 13.5 dB and 7 GHz centered at 60 GHz, respectively. The proposed LNA consumes only 11.6 mA from a 0.9-V supply voltage with an NF of 8.4 dB at 60 GHz, including the input transformer loss. The input 1 dB compression point (IP_1dB) of −15 dBm at 60 GHz confirms the first-rate linearity of the proposed amplifier. Human body model (HBM) electrostatic discharge (ESD) protection is guaranteed up to 2 kV at the RF input/output pads thanks to the input/output integrated transformers. Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

This article presents a low-noise amplifier (LNA) with high image rejection ratio (IRR) operating in the 5G millimeter-wave band using a 65 nm CMOS process. The circuit adopts an inter-stage notch filtering structure composed of a transformer and a switched capacitor array to achieve image suppression and impedance matching with no die area overhead. By adjusting the values of the switch capacitor array, the transmission zeros are positioned in the stopband while the poles are placed in the passband, thereby realizing image rejection. Furthermore, the number and distribution of poles under the both real and complex impedance conditions are analyzed. Moreover, the quality factor (Q) of the zero is derived to establish the relationship between Q and the image rejection ratio, guiding the optimization of both gain and IRR of the circuit design. Measurement results demonstrate that the LNA exhibits a gain of 18 dB and a noise figure (NF) of 4.4 dB at 40 GHz, with a corresponding IRR of 53.4 dB when the intermediate frequency (IF) is 6 GHz. The circuit demonstrates a 3 dB bandwidth from 36.3 to 40.7 GHz, with an IRR greater than 42 dB across this frequency range. The power consumption is 25.4 mW from a 1 V supply, and the pad-excluded core area of the entire chip is 0.13 mm². Full article

The global allocation of over 5 GHz of spectral bandwidth around the 60 GHz frequency band offers significant potential for ultra-high data rate wireless communication over short distances and enables the implementation of high-resolution frequency-modulated continuous-wave (FMCW) radar applications. In this study, a Front-End Receiver covering frequencies from 57 to 64 GHz was designed and characterized in a 40 nm CMOS process. The proposed architecture includes a Low-Noise Amplifier (LNA), a novel double-balanced mixer offering variable conversion gain, and a low-power class-C Voltage-Controlled Oscillator (VCO). From post-layout simulation results, the LNA presents a noise figure (NF) less than 4.8 dB and a gain more than 19 dB, while the input compression point (P1dB) reaches −15.6 dBm. The double-balanced mixer delivers a noise figure of less than 11 dB, a conversion gain of 14 dB, and an input-referred compression point of −13 dBm. The VCO achieves a phase noise of approximately −93 dBc/Hz at 1 MHz offset from 60 GHz and a tuning range of about 8 GHz, dissipating only 6.6 mW. Overall, the receiver demonstrates a maximum conversion gain of more than 39 dB, a noise figure of less than 9.2 dB, an input- referred compression point of −37 dBm, and a power dissipation of 56 mW. Full article

This paper presents an ultra-wideband low-noise amplifier (LNA) with a new cross-coupling noise-canceling technique for 28 nm CMOS technology. The entire LNA contains two stages. The first stage employs inductively coupled Gm-boosted technology, while the second stage is a novel asymmetric cross-coupling noise-canceling structure (ACCNCS). Through the introduction of these two key techniques, the LNA achieves balanced performance across a relative bandwidth of 56%. Input/output/inter-stage impedance matching uses a transformer-based network with series-parallel combinations of inductors and capacitors. The LNA is designed in a 28 nm CMOS process with a chip core area of 335 × 665 µm². The operating frequency range is 26–46 GHz. Post-layout simulation results show that the peak gain of the LNA is 12.6 dB, and the noise figure is between 2.9 and 4.2 dB across the wideband range. At a center frequency of 36 GHz with a supply voltage (V_DD) of 0.9 V, the input 1 dB compression point (IP_1dB) is −7.6 dBm, while the power consumption is 22 mW. Full article

This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other by large MIMCAPs, which results in good performance with low power consumption. The proposed circuit achieves a bandwidth of 2.5 GHz, suitable for several wireless communication standards such as GSM, WLAN, and Bluetooth. In the first stage, a current-reuse circuit with shunt feedback is used to satisfy input impedance matching and signal amplification with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve the noise figure (NF), harmonic distortion, and output impedance matching. The proposed LNA is designed in 65 nm CMOS technology and covers a frequency range of 0.17–2.68 GHz. The proposed LNA achieves a maximum gain of 17.24 dB, a minimum NF of 2.67 dB, a maximum IIP3 of −14.9 dBm, and input and output return losses of less than −10 dB. The power consumption of the proposed LNA is 3.52 mW from a 1 V power supply, and the core area is 0.3 mm². Full article

This paper presents a low-power and area-efficient chopper-stabilized low noise amplifier (CS-LNA) for in-pixel neural recording systems. The proposed CS-LNA can be used in a multi-channel architecture, in which the chopper mixers of the LNA are exploited to provide the time division multiplexing (TDM) of several channels, while reducing the flicker noise and rejecting the Electrode DC Offset (EDO). A detailed noise analysis including the effect of the chopper stabilization on flicker noise, and a design flow to optimize the trade-off between input-referred noise and silicon area are presented, and utilized to design the LNA. The adopted approach to reject the EDO allows to tolerate an input offset of ±50 mV, without appreciably affecting the CS-LNA performance, and does not require an additional DC Servo Loop (DSL). The proposed CS-LNA has been fabricated in a 0.13 μm CMOS process with an area of 0.0268 mm², consuming about 2 μA from a 0.8 V supply voltage. It achieves an integral noise of 4.19 μVrms (2.58 μVrms) from 1 to 7.5 kHz (from 300 to 7.5 kHz) and results in a noise efficiency factor (NEF) of 2.63 (1.62). Besides achieving a maximum gain of 38.67 dB with a tuning range of about 12 dB, the neural amplifier exhibits a CMRR of 67 dB. A comparison with the recent literature dealing with in-pixel amplifiers shows state-of-the-art performance. Full article

In this work, a unified design methodology for front-end RF/mmWave receivers is presented, aiming to significantly accelerate the design procedure of the front-end RF blocks in complex RX/TX chain implementations. The proposed design methodology is based on optimization loops with well-defined cost functions so as to minimize the design iterations that may be encountered during specification tuning. As proof of concept, two essential RF blocks widely used in RF receivers, a low-noise amplifier (LNA) and a voltage-controlled oscillator (VCO), were designed using the proposed unified methodology with a 65 nm RF-CMOS processing node. Finally, the derived designs were compared to similar designs in the literature, proving that the proposed unified methodology is capable of synthesizing RF/mmWave LNAs and VCOs with industry-standard specifications within a significantly faster time frame. Full article

This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. Full article

This paper proposes a highly linear low-noise amplifier (LNA) using a cascode configuration. In the proposed topology, the linearity of the circuit is enhanced through the application of derivative superposition technology. The technology combines an auxiliary transistor operating in the moderate inversion region with a main transistor operating in the strong inversion region, and two degenerative inductors are connected in series at the source nodes of both transistors. The primary objective of this design is to mitigate the negative impacts of second-order and third-order nonlinearities on the third-order input intercept point (IIP3) through their interactions, thereby enhancing the linear performance of the circuit. An on-chip active bias circuit is designed to effectively address fluctuations in the IIP3 during process and temperature variations by stabilizing the transconductance of the common-source transistor, enabling the LNA to operate reliably in complex environments. During post-layout simulation in DongBu High-Tech’s 0.13 μm CMOS process, the circuit’s output third-order intercept point (OIP3) exhibits minimal fluctuations across different process corners and temperature variations. At the typical nmos and typical pmos (TT) process corner and a temperature of 30 °C, it achieves an OIP3 of 33.9 dBm with a power consumption of 42 mW sourced from a 2.8 V power supply. Furthermore, it realizes a relatively flat gain of 16 dB, a noise figure (NF) of 0.91 dB, input return loss less than −8 dB, and output return loss less than −10 dB. Full article

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP_1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection. Full article

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively. Full article

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA’s temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier’s bandwidth. Over the wide temperature range of −55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At −55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm², including all test pads, while the core area is only 0.09 mm². Full article

An adaptive Nesterov quasi-Newton acceleration (an-QNA)-optimized low-noise amplifier (LNA) is proposed in this paper. An optimized single-ended-to-differential two-stage LNA circuit is presented. It includes an improved post-linearization (I_PL) technique to enhance the linearity. Traditional methods like conventional quasi-Newton (c-QN) often suffer from slow convergence and the tendency to get trapped in local minima. However, the proposed an-QNA method significantly accelerates the convergence speed. Furthermore, in this paper, modifications have been made to the an-QNA algorithm using a quadratic estimation to guarantee global convergence. The optimized an-QNA-based LNA, using standard 65 nm CMOS technology, achieves a simulated gain of 17.5 dB, a noise figure (NF) of 3.7 dB, and a 1 dB input compression point (IP₁dB) of −13.1 dBm. It is also noted that the optimized LNA achieves a measured gain of 12.9 dB and an NF of 4.98 dB, and the IP₁dB is −17.8 dB. The optimized LNA has a chip area of 0.67 mm². Full article