Search Results (24)

To address the performance and power concerns in Double-Data-Rate SDRAM (DDR) subsystems, this paper presents an innovative method for the DDR memory controller scheduler. This design aims to strike a balance between power consumption and performance for the DDR subsystem. Our approach entails a critical reassessment of established mechanisms and the introduction of a quasi-static arbitration protocol for the DDR’s low-power mode (LPM) transition processes. Central to our proposed DDR power-management framework is the Low-Power-Management Engine (LPME), complemented by a suite of statistical algorithms tailored for implementation within the architecture. Our research strategy encompasses real-time monitoring of the DDR subsystem’s operational states, traffic intervals, and Quality of Service (QoS) metrics. By dynamically fine-tuning the DDR subsystem’s power-management protocols to transition in and out of identical power modes, our method promises substantial enhancements in both energy efficiency and operational performance across a spectrum of practical scenarios. To substantiate the efficacy of our proposed design, an array of experiments was conducted. These rigorous tests evaluated the DDR subsystem’s performance and energy consumption under a diverse set of workloads and system configurations. The findings are compelling: the LPME-driven architecture delivers significant power savings of over 41%, concurrently optimizing performance metrics like latency increase by no more than 22% in a high-performance operational context. Full article

Emerging applications like deep neural networks require high off-chip memory bandwidth and low dynamic loaded Double Data Rate SDRAM (DDR) latency. However, under the stringent physical constraints of chip packages and system boards, it is extremely expensive to further increase the bandwidth and reduce the dynamic loaded latency of off-chip memory in terms of DDR devices. To address the latency issues in DDR subsystems, this paper presents a novel architecture aiming at achieving latency optimization through a use case sensitive controller. We propose a reevaluation of conventional decoupling mechanisms and quasi-static arbitration methods in the DDR scheduling architecture. The adaptive scheduling algorithms offer significant advantages in various real-world scenarios. The research methodology involves implementing a rank-level timing aware read/write turnaround arbiter and setting read/write queue thresholds and read/write turnaround settings based on observed patterns. By implementing the arbiter and dynamically adjusting these parameters, the proposed architecture aims to optimize the performance of the DDR subsystem. To validate the effectiveness of the architecture, we conduct multiple experiments. These experiments evaluate the performance of the DDR subsystem under various workloads and configurations. The results demonstrate that the adaptive scheduling algorithms have advantages in achieving DDR performance attributes for workloads and improving system performance. The experimental results provide evidence of the architecture’s effectiveness in reducing latency by around 10% to 50% in various real-world scenarios. Full article

This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration—on the row hammer effect (RHE) in DRAM cells. The influence of adjacent and passing gates on the DRAM cell body potential was identified as a key factor in D0 and D1 failures. The tolerance for D1 and D0 failures was analyzed, defined as the threshold number of pulses required to induce a 0.6 V change in the storage node voltage (from 1.2 V to 0.6 V for a D1 failure or from 0 V to 0.6 V for a D0 failure). D1 (D0) failure tolerances with the slope from the top of the top gate (θ_angle) of 3°, the height of the TiN gate covering the fin (H_{fin_overlap}) of 12.5 nm, and the height of the fin (H_fin) of 12.5 nm are 1.26 × 10⁶ (4.8 × 10⁶), 1.14 × 10⁶ (4 × 10⁷), and 7.5 × 10⁵ (4.8 × 10⁵), respectively. Higher θ_angles and smaller fin heights generally result in higher RHE tolerances. Although decreasing the fin height reduced the RHE, it also decreased the on-current and resulted in an increase in the threshold voltage (V_T) and the subthreshold swing (SS). In addition, by increasing the substrate bottom doping concentration (P_{dop_bot}), we improve RHE tolerance twice its original level without reducing the on-current. Therefore, designing a buried channel array transistor (BCAT) structure requires careful consideration of these trade-offs, and a thorough understanding of the underlying mechanism is crucial to devising strategies that reduce RHE tolerance. The findings of this study are expected to contribute significantly to the development of next-generation DRAM architectures, enhancing stability and performance. By addressing the reliability challenges posed by advanced scaling, this study paves the way for the ongoing advancement of DRAM technology for high-density and high-performance applications. Full article

Information-Centric Networking (ICN) typically utilizes DRAM (Dynamic Random Access Memory) to build in-network cache components due to its high data transfer rate and low latency. However, DRAM faces significant limitations in terms of cost and capacity, making it challenging to meet the growing demands for cache scalability required by increasing Internet traffic. Combining high-speed but expensive memory (e.g., DRAM) with large-capacity, low-cost storage (e.g., SSD) to construct a hierarchical cache architecture has emerged as an effective solution to this problem. However, how to perform efficient cache management in such architectures to realize the expected cache performance remains challenging. This paper proposes a cache management scheme for hierarchical cache architectures in ICN, which introduces a differentiated replica replacement policy to accommodate the varying request access patterns at different cache layers, thereby enhancing overall cache performance. Additionally, a probabilistic insertion-based SSD cache admission filtering mechanism is designed to control the SSD write load, addressing the issue of balancing SSD lifespan and space utilization. Extensive simulation results demonstrate that the proposed scheme exhibits superior cache performance and lower SSD write load under various workloads and replica placement strategies, highlighting its broad applicability to different application scenarios. Additionally, it maintains stable performance improvements across different cache capacity settings, further reflecting its good scalability. Full article

Halogenated boroxine K₂[B₃O₃F₄OH] (HB), an inorganic derivative of cyclic anhydride of boronic acid, is patented as a boron-containing compound with potential for the treatment of both benign and malignant skin changes. HB has effectively inhibited the growth of several carcinoma cell lines. Because of the growing interest in autophagy induction as a therapeutic approach in bladder carcinoma (BC), we aimed to assess the effects of HB on metabolic phenotype and autophagy levels in 5637 human bladder carcinoma cells (BC). Cytotoxicity was evaluated using the alamar blue assay, and the degree of autophagy was determined microscopically. Mitochondrial respiration and glycolysis were measured simultaneously. The relative expression of autophagy-related genes BECN1, P62, BCL-2, and DRAM1 was determined by real-time PCR. HB affected cell growth, while starvation significantly increased the level of autophagy in the positive control compared to the basal level of autophagy in the untreated negative control. In HB-treated cultures, the degree of autophagy was higher compared to the basal level, and metabolic phenotypes were altered; both glycolysis and oxidative phosphorylation (OXPHOS) were decreased by HB at 0.2 and 0.4 mg/mL. Gene expression was deregulated towards autophagy induction and expansion. In conclusion, HB disrupted the bioenergetic metabolism and reduced the intracellular survival potential of BC cells. Further molecular studies are needed to confirm these findings and investigate their applicative potential. Full article

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F² DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V. Full article

Semiconductor manufacturing is a complex and lengthy process. Even with their expertise and experience, engineers often cannot quickly identify anomalies in an extensive database. Most research into equipment combinations has focused on the manufacturing process’s efficiency, quality, and cost issues. There has been little consideration of the relationship between semiconductor station and equipment combinations and throughput. In this study, a machine learning approach that allows for the integration of control charts, clustering, and association rules were developed. This approach was used to identify equipment combinations that may harm production processes by analyzing the effect on Vt parameters of the equipment combinations used in wafer acceptance testing (WAT). The results showed that when the support is between 70% and 80% and the confidence level is 85%, it is possible to quickly select the specific combinations of 13 production stations that significantly impact the Vt values of all 39 production stations. Stations 046000 (EH308), 049200 (DW005), 049050 (DI303), and 060000 (DC393) were found to have the most abnormal equipment combinations. The results of this research will aid the detection of equipment errors during semiconductor manufacturing and assist the optimization of production scheduling. Full article

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10⁻²² A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it’s essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al₂O₃ gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/−1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al₂O₃ gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at −0.73~−0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al₂O₃ dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process. Full article

High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (T_L), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. T_L was indirectly controlled by the heatsink temperature (T_S). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at T_L of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the T_L temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the T_L temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s. Full article

Mitochondria are essential organelles and crucial for cellular survival. Mitochondrial biogenesis and mitophagy are dynamic features that are essential for both maintaining the health of the mitochondrial network and cellular demands. The accumulation of damaged mitochondria has been shown to be related to a wide range of pathologies ranging from neurological to musculoskeletal. Mitophagy is the selective autophagy of mitochondria, eliminating dysfunctional mitochondria in cells by engulfment within double-membraned vesicles. Preeclampsia and low birth weight constitute prenatal complications during pregnancy and are leading causes of maternal and fetal mortality and morbidity. Both placental implantation and fetal growth require a large amount of energy, and a defect in the mitochondrial quality control mechanism may be responsible for the pathophysiology of these diseases. In this review, we compiled current studies investigating the role of BNIP3, DRAM1, and FUNDC1, mediators of receptor-mediated mitophagy, in the progression of preeclampsia and the role of mitophagy pathways in the pathophysiology of low birth weight. Recent studies have indicated that mitochondrial dysfunction and accumulation of reactive oxygen species are related to preeclampsia and low birth weight. However, due to the lack of studies in this field, the results are controversial. Therefore, mitophagy-related pathways associated with these pathologies still need to be elucidated. Mitophagy-related pathways are among the promising study targets that can reveal the pathophysiology behind preeclampsia and low birth weight. Full article

The emergence of different virus variants, the rapidly changing epidemic, and demands for economic recovery all require continual adjustment and optimization of COVID-19 intervention policies. For the purpose, it is both important and necessary to evaluate the effectiveness of different policies already in-place, which is the basis for optimization. Although some scholars have used epidemiological models, such as susceptible-exposed-infected-removed (SEIR), to perform evaluation, they might be inaccurate because those models often ignore the time-varying nature of transmission rate. This study proposes a new scheme to evaluate the efficiency of dynamic COVID-19 interventions using a new model named as iLSEIR-DRAM. First, we improved the traditional LSEIR model by adopting a five-parameter logistic function $\beta \left(t\right)$ to depict the key parameter of transmission rate. Then, we estimated the parameters by using an adaptive Markov Chain Monte Carlo (MCMC) algorithm, which combines delayed rejection and adaptive metropolis samplers (DRAM). Finally, we developed a new quantitative indicator to evaluate the efficiency of COVID-19 interventions, which is based on parameters in $\beta \left(t\right)$ and considers both the decreasing degree of the transmission rate and the emerging time of the epidemic inflection point. This scheme was applied to seven cities in Guangdong Province. We found that the iLSEIR-DRAM model can retrace the COVID-19 transmission quite well, with the simulation accuracy being over 95% in all cities. The proposed indicator succeeds in evaluating the historical intervention efficiency and makes the efficiency comparable among different cities. The comparison results showed that the intervention policies implemented in Guangzhou is the most efficient, which is consistent with public awareness. The proposed scheme for efficiency evaluation in this study is easy to implement and may promote precise prevention and control of the COVID-19 epidemic. Full article

With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage, leading to sensing failure. Previous studies indicate that the threshold voltage mismatch between the paired transistors of a sense amplifier is the most critical factor. In this study, virtual wafers were generated, including statistical V_T variation. Then, we numerically investigate the prediction accuracy and reliability of the offset voltage of DRAM wafers using test point measurement for the first time. We expect that this study will be helpful in strengthening the in-line controllability of wafers to secure the DRAM sensing margin. Full article

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters. Full article

The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip memory has provided new opportunities to rethink traditional memory hierarchies and their management. In this study, we propose a polymorphic memory as a hybrid approach when using on-chip memory. In contrast to previous studies, we use the on-chip memory as both a main memory (called M1 memory) and a Dynamic Random Access Memory (DRAM) cache (called M2 cache). The main memory consists of M1 memory and a conventional DRAM memory called M2 memory. To achieve high performance when running many applications on this memory architecture, we propose management techniques for the main memory with M1 and M2 memories and for polymorphic memory with dynamic memory allocations for many applications in a manycore system. The first technique is to move frequently accessed pages to M1 memory via hardware monitoring in a memory controller. The second is M1 memory partitioning to mitigate contention problems among many processes. Finally, we propose a method to use M2 cache between a conventional last-level cache and M2 memory, and we determine the best cache size for improving the performance with polymorphic memory. The proposed schemes are evaluated with the SPEC CPU2006 benchmark, and the experimental results show that the proposed approaches can improve the performance under various workloads of the benchmark. The performance evaluation confirms that the average performance improvement of polymorphic memory is 21.7%, with 0.026 standard deviation for the normalized results, compared to the previous method of using on-chip memory as a last-level cache. Full article

Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by the increasingly difficult task of sensing cell data reliably. One of the essential methods to preserve sustainable data retention characteristic is to curtail the sub-threshold leakage current by using a negative voltage bias for the bulk of access transistors. This negative back-bias is generated by a back-bias voltage generator. This paper proposes a novel high-speed back-bias voltage (VBB) generator with a cross-coupled hybrid pumping scheme. The conventional circuit uses one fixed voltage to control the gates of discharge of the p-channel metal oxide semiconductor (PMOS) and transfer n-channel metal oxide semiconductor (NMOS), respectively. However, the proposed circuit adds an auxiliary pump, thereby able to control more aptly with a lower negative voltage when discharging and a higher positive voltage when transferring. As a result, the proposed circuit achieves a faster pump-down speed and higher pumping current at a lower supply voltage compared to conventional circuits. The H-simulation program with integrated circuit emphasis (HSPICE) simulation results with the Taiwan semiconductor manufacturing company (TSMC) 0.18 um process technology indicates that the proposed circuit has about a 20% faster pump-down speed at a supply voltage of voltage common collector (VCC) = 1.2 V and about 3% higher pumping current at VBB from −0.6 V to −1 V with the ability to generate a near 3% higher ratio of |VBB|/VCC at VCC = 0.6 V compared to conventional circuits. Hence, the proposed circuit is extremely suitable and promising for future low-power and high-performance DRAM applications. Full article