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J. Low Power Electron. Appl., Volume 2, Issue 1 (March 2012), Pages 1-126

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Research

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Open AccessArticle CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors
J. Low Power Electron. Appl. 2012, 2(1), 30-68; doi:10.3390/jlpea2010030
Received: 20 October 2011 / Revised: 18 January 2012 / Accepted: 23 January 2012 / Published: 1 February 2012
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Abstract
Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs). While most chip [...] Read more.
Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs). While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9 instruction set enabling them to run a full operating system software stack, and hence a wide variety of benchmarking applications. Full article
(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
Open AccessArticle Short-Circuit Power Reduction by Using High-Threshold Transistors
J. Low Power Electron. Appl. 2012, 2(1), 69-78; doi:10.3390/jlpea2010069
Received: 15 October 2011 / Revised: 13 February 2012 / Accepted: 21 February 2012 / Published: 1 March 2012
Cited by 3 | PDF Full-text (573 KB) | HTML Full-text | XML Full-text
Abstract
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic [...] Read more.
In this brief paper, the dependency of short-circuit power on threshold voltage is analyzed and utilized for short circuit (SC) power reduction in multi-threshold (MTCMOS) processes. Analytical expressions are developed for estimation of the change of ratio between short-circuit power and dynamic power (PSC/Pdyn) while changing the design process. The analysis shows that the PSC/Pdyn ratio can increase significantly if the VT/Vdd ratio in new process decreases. An analytical expression is also derived for estimation of potential SC power reduction in MTCMOS processes by replacing low-VT transistors by high-VT devices in the same process. The proposed technique allows significant reduction of SC power without the need for process shift. The simulation results show good correlation with the analytical estimation at cell level, while demonstrating an average SC power saving of 36%. The performance impact is also validated, showing that timing degradation is minor and controllable. The proposed optimization technique is applicable to any multi-threshold process. The technique is simple for implementation, and can be easily integrated in the existing optimization tools. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Open AccessArticle Multi-Functional Micro Projection Device as Screen Substitute for Low Power Consumption Computing
J. Low Power Electron. Appl. 2012, 2(1), 79-97; doi:10.3390/jlpea2010079
Received: 20 December 2011 / Revised: 20 February 2012 / Accepted: 21 February 2012 / Published: 5 March 2012
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Abstract
One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in [...] Read more.
One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the development of low power consumption computing systems. In this paper we present one possible solution involving micro projection device based upon lasers and a digital light processing (DLP) matrix which is a matrix of electrically controllable mirrors capable of translating electrical signal to a time varying projected image. It can serve to substitute a screen and consume ten times less power than a conventional screen. The described device is a multifunctional highly efficient customized DLP light engine being capable of serving as an image projector and simultaneously to support range and topography estimation measurements. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Open AccessArticle Analysis of Dynamic Differential Swing Limited Logic for Low-Power Secure Applications
J. Low Power Electron. Appl. 2012, 2(1), 98-126; doi:10.3390/jlpea2010098
Received: 28 December 2011 / Revised: 2 March 2012 / Accepted: 2 March 2012 / Published: 16 March 2012
Cited by 3 | PDF Full-text (392 KB)
Abstract
Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A [...] Read more.
Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A complete analysis of an advanced encryption standard (AES) S-box is conducted using a low-power (LP) 65 nm CMOS technology node. Measurements show that the DDSLL S-box has 35% less power consumption than the static CMOS S-box, with an area increase of only 12%, at the expense of a 2.5× increase in delay which remains fairly acceptable for low-power applications such as RFIDs and smart cards. Also when compared to other dynamic differential logic (DDL) styles, simulation results show that DDSLL and dynamic current mode logic (DyCML) consume the same power which is about 1.8× less that of sense amplifier based logic (SABL). The effect of process variations is also studied, measurement results show that the DDSLL style has lower variability in terms of dynamic power as the activity factor (αF) is deterministic thanks to glitch-free operation. As for security, the perceived information metric demonstrates that the DDSLL S-box has a 3× security margin compared to static CMOS. Therefore, DDSLL presents an interesting tradeoff between improved security and area constrained low-power designs. Full article
(This article belongs to the Special Issue Low Power Electronics - Recent Developments)

Review

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Open AccessReview CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
J. Low Power Electron. Appl. 2012, 2(1), 1-29; doi:10.3390/jlpea2010001
Received: 12 December 2011 / Revised: 14 January 2012 / Accepted: 16 January 2012 / Published: 27 January 2012
Cited by 10 | PDF Full-text (2808 KB) | HTML Full-text | XML Full-text
Abstract
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration [...] Read more.
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed. Full article
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)

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