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J. Low Power Electron. Appl., Volume 2, Issue 2 (June 2012), Pages 127-196

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Research

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Open AccessArticle VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy
J. Low Power Electron. Appl. 2012, 2(2), 127-142; doi:10.3390/jlpea2020127
Received: 31 December 2011 / Revised: 22 March 2012 / Accepted: 26 March 2012 / Published: 29 March 2012
Cited by 7 | PDF Full-text (151 KB)
Abstract
A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, [...] Read more.
A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α† = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α† = 4.5958 for an 8% reduction in total power (PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy. Full article
(This article belongs to the Special Issue Low Power Electronics - Recent Developments)
Open AccessArticle 0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process
J. Low Power Electron. Appl. 2012, 2(2), 155-167; doi:10.3390/jlpea2020155
Received: 15 March 2012 / Revised: 8 May 2012 / Accepted: 8 May 2012 / Published: 18 May 2012
PDF Full-text (1253 KB) | HTML Full-text | XML Full-text
Abstract
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input [...] Read more.
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
Open AccessArticle Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation
J. Low Power Electron. Appl. 2012, 2(2), 168-179; doi:10.3390/jlpea2020168
Received: 7 March 2012 / Revised: 7 May 2012 / Accepted: 8 May 2012 / Published: 24 May 2012
Cited by 3 | PDF Full-text (556 KB) | HTML Full-text | XML Full-text | Correction | Supplementary Files
Abstract
A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( < Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
Open AccessArticle Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS
J. Low Power Electron. Appl. 2012, 2(2), 180-196; doi:10.3390/jlpea2020180
Received: 2 March 2012 / Revised: 29 May 2012 / Accepted: 30 May 2012 / Published: 6 June 2012
Cited by 9 | PDF Full-text (621 KB) | HTML Full-text | XML Full-text
Abstract
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this [...] Read more.
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)
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Review

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Open AccessReview Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN
J. Low Power Electron. Appl. 2012, 2(2), 143-154; doi:10.3390/jlpea2020143
Received: 16 February 2012 / Revised: 6 April 2012 / Accepted: 11 April 2012 / Published: 18 April 2012
Cited by 3 | PDF Full-text (296 KB) | HTML Full-text | XML Full-text
Abstract
The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes [...] Read more.
The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write VMIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4–13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the unassisted test case. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2011 Conference)

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