Search Results (46)

Three-dimensional trench electrode silicon detectors play an important role in particle physics research, nuclear radiation detection, and other fields. A novel polysilicon-fill-strengthened etch-through 3D trench electrode detector is proposed to address the shortcomings of traditional 3D trench electrode silicon detectors; for example, the distribution of non-uniform electric fields, asymmetric electric potential, and dead zone. The physical properties of the detector have been extensively and systematically studied. This study simulated the electric field, potential, electron concentration distribution, complete depletion voltage, leakage current, capacitance, transient current induced by incident particles, and weighting field distribution of the detector. It also systematically studied and analyzed the electrical characteristics of the detector. Compared to traditional 3D trench electrode silicon detectors, this new detector adopts a manufacturing process of double-side etching technology and double-side filling technology, which results in a more sensitive detector volume and higher electric field uniformity. In addition, the size of the detector unit is 120 µm × 120 µm × 340 µm; the structure has a small fully depleted voltage, reaching a fully depleted state at around 1.4 V, with a saturation leakage current of approximately $4.8\times {10}^{-10}\mathrm{A}$, and a geometric capacitance of about 99 fF. Full article

In this study, we develop a graphene-trenched silicon Schottky junction for humidity sensing. This novel structure comprises suspended graphene bridging etched trenches on a silicon substrate, creating both free-standing and substrate-contacting regions of graphene that enhance water adsorption sensing. Suspended graphene is intrinsically insensitive to water adsorption, making it difficult for adsorbed H₂O to effectively dope the graphene. In contrast, when graphene is supported on the silicon substrate, water molecules can effectively dope the graphene by modifying the silicon’s impurity bands and their hybridization with graphene. This humidity-induced doping leads to a significant modulation of the Schottky barrier at the graphene–silicon interface, which serves as the core sensing mechanism. We investigate the current–voltage (I–V) characteristics of these devices as a function of trench width and relative humidity. Our analysis shows that humidity influences key device parameters, including the Schottky barrier height, ideality factor, series resistance, and normalized sensitivity. Specifically, larger trench widths reduce the graphene density of states, an effect that is accounted for in our analysis of these parameters. The sensor operates under both forward and reverse bias, enabling tunable sensitivity, high selectivity, and low power consumption. These features make it promising for applications in industrial and home safety, environmental monitoring, and process control. Full article

Dynamic random-access memory (DRAM) is a vital component in modern computing systems. Enhancing memory performance requires maximizing capacitor capacitance within DRAM cells, which is achieved using high-k dielectric materials deposited as thin, uniform films via atomic layer deposition (ALD). Precise film deposition that minimizes electronic defects caused by charged vacancies is essential for reducing leakage current and ensuring high dielectric strength. In this study, we fabricated metal–insulator–metal (MIM) capacitors in high-aspect-ratio trench structures using remote plasma ALD (RP-ALD) and direct plasma ALD (DP-ALD). The trenches, etched into silicon, featured a 7:1 aspect ratio, 76 nm pitch, and 38 nm critical dimension. We evaluated the electrical characteristics of HfO₂-based capacitors with TiN top and bottom electrodes, focusing on leakage current density and equivalent oxide thickness. Capacitance–voltage analysis and X-ray photoelectron spectroscopy (XPS) revealed that RP-ALD effectively suppressed plasma-induced damage, reducing defect density and leakage current. While DP-ALD offered excellent film properties, it suffered from degraded lateral uniformity due to direct plasma exposure. Given its superior lateral uniformity, lower leakage, and defect suppression, RP-ALD shows strong potential for improving DRAM capacitor performance and serves as a promising alternative to the currently adopted thermal ALD process. Full article

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (R_DS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in R_DS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in R_DS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs. Full article

Falling within the safe bands for human eyes, 1550 nm semiconductor lasers have a wide range of applications in the fields of LIDAR, fast-ranging long-distance optical communication, and gas sensing. The 1550 nm human eye-safe high-power tunnel junction quantum well laser developed in this paper uses three quantum well structures connected by two tunnel junctions as the active region; photolithography and etching were performed to form two trenches perpendicular to the direction of the epitaxial layer growth with a depth exceeding the tunnel junction, and the trenches were finally filled with oxides to reduce the extension current. Finally, a 1550 nm InGaAlAs quantum well laser with a pulsed peak power of 31 W at 30 A (10 KHz, 100 ns) was realized for a single-emitter laser device with an injection strip width of 190 μm, a ridge width of 300 μm, and a cavity length of 2 mm, with a final slope efficiency of 1.03 W/A, and with a horizontal divergence angle of about 13° and a vertical divergence angle of no more than 30°. The device has good slope efficiency, and this 100 ns pulse width can be effectively applied in the fields of fog-transparent imaging sensors and fast headroom ranging radar areas. Full article

Microfabrication technology with quartz crystals is gaining importance as the miniaturization of quartz MEMS devices is essential to ensure the development of portable and wearable electronics. However, until now, there have been no reports of dimension compensation for quartz device fabrication. Therefore, this paper studied the wet etching process of Z-cut quartz crystal substrates for making deep trench patterns using Au/Cr metal hard masks and proposed the first quartz fabrication dimension compensation strategy. The size effect of various sizes of hard mask patterns on the undercut developed in wet etching was experimentally investigated. Quartz wafers masked with initial vias ranging from 3 μm to 80 μm in width were etched in a buffered oxide etch solution (BOE, HF:NH₄F = 3:2) at 80 °C for prolonged etching (>95 min). It was found that a larger hard mask width resulted in a smaller undercut, and a 30 μm difference in hard mask width would result in a 17.2% increase in undercut. In particular, the undercuts were mainly formed in the first 5 min of etching with a relatively high etching rate of 0.7 μm/min (max). Then, the etching rate decreased rapidly to 27%. Furthermore, based on the etching width compensation and etching position compensation, new solutions were proposed for quartz crystal device fabrication. And these two kinds of compensation solutions were used in the fabrication of an ultra-small quartz crystal tuning fork with a resonant frequency of 32.768 kHz. With these approaches, the actual etched size of critical parts of the device only deviated from the designed size by 0.7%. And the pattern position symmetry of the secondary lithography etching process was improved by 96.3% compared to the uncompensated one. It demonstrated significant potential for improving the fabrication accuracy of quartz crystal devices. Full article

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (tr_pbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (T_SD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (C_gg) as the T_SD increases. A higher TIS height prevents the C_gg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (C_L) increases. As C_L increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling tr_pbt and improving electro-thermal performance in sub-3 nm node NSFETs. Full article

We report the design, fabrication, and characterization of hollow-core anti-resonant reflecting optical waveguides (ARROWs) fabricated in a membrane-covered trench. These structures are built on silicon wafers using standard microfabrication techniques, including plasma etching, to form trenches. Four waveguide designs are demonstrated, which have different numbers of thin-film reflecting layers. We demonstrate that optical loss decreases with additional reflecting layers, with measured loss coefficients as low as 1 cm⁻¹. Full article

We demonstrate the growth of 3C-SiC with reduced planar defects on a micro-scale compliant substrate. Heteroepitaxial growth of 3C-SiC on trenches with a width and separation of 2 µm, etched into a Si(001) substrate, is found to suppress defect propagation through the epilayer. Stacking faults and other planar defects are channeled away from the center of the patterned structures, which are rounded through the use of H₂ annealing at 1100 °C. Void formation between the columns of 3C-SiC growth acts as a termination point for defects, and coalescence of these columns into a continuous epilayer is promoted through the addition of HCl in the growth phase. The process of fabricating these compliant substrates utilizes standard processing techniques found within the semiconductor industry and is independent of the substrate orientation and offcut. Full article

This study investigated the effect of temperature on the aspect-ratio etching of SiO₂ in CF₄/H₂/Ar plasma using patterned samples of a 200 nm trench in a low-temperature reactive-ion etching system. Lower temperatures resulted in higher etch rates and aspect ratios for SiO₂. However, the plasma property was constant with the chuck temperature, indicated by the line intensity ratio from optical emission spectroscopy monitoring of the plasma. The variables obtained from the characterization of the etched profile for the 200 nm trench after etching were analyzed as a function of temperature. A reduction in the necking ratio affected the etch rate and aspect ratio of SiO₂. The etching mechanism of the aspect ratio etching of SiO₂ was discussed based on the results of the surface composition at necking via energy-dispersive X-ray spectroscopy with temperature. The results suggested that the neutral species reaching the etch front of SiO₂ had a low sticking coefficient. The bowing ratio decreased with lowering temperature, indicating the presence of directional ions during etching. Therefore, a lower temperature for the aspect ratio etching of SiO₂ could achieve a faster etch rate and a higher aspect ratio of SiO₂ via the reduction of necking than higher temperatures. Full article

β-Ga₂O₃ Schottky barrier diodes (SBDs) suffer from the electric field crowding and barrier height lowering effect, resulting in a low breakdown voltage (BV) and high reverse leakage current. Here, we developed β-Ga₂O₃ trench MOS-type Schottky barrier diodes (TMSBDs) on β-Ga₂O₃ single-crystal substrates with halide vapor phase epitaxial layers based on ultraviolet lithography and dry etching. The $1/C^2-V$ plots are deflected at 2.24 V, which is caused by the complete depletion in the mesa region of the TMSBDs. A close-to-unity ideality factor of 1.02 and a low turn-on voltage of 0.72 V are obtained. This is due to the low interface trap density in the metal/semiconductor interface of TMSBDs, as confirmed by the current–voltage ($I–V$) hysteresis measurements. The specific on-resistance calculated with the actual Schottky contact area increases as the area ratio ($AR$) increases because of the current spreading phenomenon. Furthermore, the reverse leakage current of the TMSBDs is smaller and the BV is increased by 120 V compared with the regular SBD. This work paves the way for further improving the overall performance of β-Ga₂O₃ TMSBDs. Full article

Pixelated low-gain avalanche diodes (LGADs) can provide both precision spatial and temporal measurements for charged particle detection; however, electrical termination between the pixels yields a no-gain region, such that the active area or fill factor is not sufficient for small pixel sizes. Trench-isolated LGADs (TI-LGADs) are a strong candidate for solving the fill-factor problem, as the p-stop termination structure is replaced by isolated trenches etched in the silicon itself. In the TI-LGAD process, the p-stop termination structure, typical of LGADs, is replaced by isolating trenches etched in the silicon itself. This modification substantially reduces the size of the no-gain region, thus enabling the implementation of small pixels with an adequate fill factor value. In this article, a systematic characterization of the TI-RD50 production, the first of its kind entirely dedicated to the TI-LGAD technology, is presented. Designs are ranked according to their measured inter-pixel distance, and the time resolution is compared against the regular LGAD technology. Full article

In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF₆/CHF₃ proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF₃ flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication. Full article

As the process complexity has been increased to overcome challenges in plasma etching, individual control of internal plasma parameters for process optimization has attracted attention. This study investigated the individual contribution of internal parameters, the ion energy and flux, on high-aspect ratio SiO${}_2$ etching characteristics for various trench widths in a dual-frequency capacitively coupled plasma system with Ar/C${}_4$F${}_8$ gases. We established an individual control window of ion flux and energy by adjusting dual-frequency power sources and measuring the electron density and self-bias voltage. We separately varied the ion flux and energy with the same ratio from the reference condition and found that the increase in ion energy shows higher etching rate enhancement than that in the ion flux with the same increase ratio in a 200 nm pattern width. Based on a volume-averaged plasma model analysis, the weak contribution of the ion flux results from the increase in heavy radicals, which is inevitably accompanied with the increase in the ion flux and forms a fluorocarbon film, preventing etching. At the 60 nm pattern width, the etching stops at the reference condition and it remains despite increasing ion energy, which implies the surface charging-induced etching stops. The etching, however, slightly increased with the increasing ion flux from the reference condition, revealing the surface charge removal accompanied with conducting fluorocarbon film formation by heavy radicals. In addition, the entrance width of an amorphous carbon layer (ACL) mask enlarges with increasing ion energy, whereas it relatively remains constant with that of ion energy. These findings can be utilized to optimize the SiO${}_2$ etching process in high-aspect ratio etching applications. Full article

Micro-optical gyroscopes (MOGs) place a range of components of the fiber-optic gyroscope (FOG) onto a silicon substrate, enabling miniaturization, low cost, and batch processing. MOGs require high-precision waveguide trenches fabricated on silicon instead of the ultra-long interference ring of conventional F OGs. In our study, the Bosch process, pseudo-Bosch process, and cryogenic etching process were investigated to fabricate silicon deep trenches with vertical and smooth sidewalls. Different process parameters and mask layer materials were explored for their effect on etching. The effect of charges in the Al mask layer was found to cause undercut below the mask, which can be suppressed by selecting proper mask materials such as SiO₂. Finally, ultra-long spiral trenches with a depth of 18.1 μm, a verticality of 89.23°, and an average roughness of trench sidewalls less than 3 nm were obtained using a cryogenic process at −100 °C. Full article