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Miniaturized Transistors, Volume II
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Miniaturized Transistors, Volume II

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (31 March 2020) | Viewed by 99172

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editors

Dr. Lado Filipovic

E-Mail Website
Guest Editor
Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Wien, Austria
Interests: integrated sensors; 2D material sensors; semiconductor metal oxide gas sensors; 3D integration; process TCAD
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Tibor Grasser

E-Mail Website
Guest Editor
Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Wien, Austria
Interests: transistor reliability; bias temperature instability; hot carrier degradation; degradation phenomena in emerging devices; modeling and simulation of semiconductor devices
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices, stacked nanowires and nanosheets to single electron transistors, two-dimensional semiconductors and III-V devices, a torrent of research is being carried out in order to design the next transistor generations, engineer optimal materials, improve the fabrication technology, and properly model future devices. Furthermore, designing appropriate Ohmic contacts and metalization for these novel devices is no small feat and will require an in-depth look at new conducting materials, dielectrics, and innovative designs. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles which focus on trends in micro- and nanotechnology from fundamental research to applications.

Dr. Lado Filipovic
Prof. Dr. Tibor Grasser
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CMOS transistor scaling
  • Advanced More Moore devices and circuits
  • Nano-scale devices
    • Nanoelectronics
    • Nanostructures
    • Quantum information processing
    • Quantum physics
    • Quantum transport Emerging devices and memories
  • Fabrication of modern devices and interconnects
  • Metalization
  • Back end of line reliability
  • Process reliability and variability
  • Modeling and simulation of semiconductor processes and devices
  • Compact modeling
  • Circuit simulation

Published Papers (23 papers)

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Editorial

Jump to: Research, Review

4 pages, 172 KiB  
Editorial
Special Issue on Miniaturized Transistors, Volume II
by Lado Filipovic and Tibor Grasser
Micromachines 2022, 13(4), 603; https://doi.org/10.3390/mi13040603 - 12 Apr 2022
Cited by 1 | Viewed by 1194
Abstract
Due to the great success of the initial Special Issue on Miniaturized Transistors [...] Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)

Research

Jump to: Editorial, Review

12 pages, 3074 KiB  
Article
150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers
by Feng-Tso Chien, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen and Hsien-Chin Chiu
Micromachines 2020, 11(5), 504; https://doi.org/10.3390/mi11050504 - 15 May 2020
Cited by 6 | Viewed by 6100
Abstract
A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT [...] Read more.
A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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11 pages, 1008 KiB  
Article
Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors
by Bernhard Stampfer, Franz Schanovsky, Tibor Grasser and Michael Waltl
Micromachines 2020, 11(4), 446; https://doi.org/10.3390/mi11040446 - 23 Apr 2020
Cited by 9 | Viewed by 2263
Abstract
Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in [...] Read more.
Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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15 pages, 5643 KiB  
Article
Simulation Study of Surface Transfer Doping of Hydrogenated Diamond by MoO3 and V2O5 Metal Oxides
by Joseph McGhee and Vihar P. Georgiev
Micromachines 2020, 11(4), 433; https://doi.org/10.3390/mi11040433 - 20 Apr 2020
Cited by 9 | Viewed by 4599
Abstract
In this work, we investigate the surface transfer doping process that is induced between hydrogen-terminated (100) diamond and the metal oxides, MoO3 and V2O5, through simulation using a semi-empirical Density Functional Theory (DFT) method. DFT was used to [...] Read more.
In this work, we investigate the surface transfer doping process that is induced between hydrogen-terminated (100) diamond and the metal oxides, MoO3 and V2O5, through simulation using a semi-empirical Density Functional Theory (DFT) method. DFT was used to calculate the band structure and charge transfer process between these oxide materials and hydrogen terminated diamond. Analysis of the band structures, density of states, Mulliken charges, adsorption energies and position of the Valence Band Minima (VBM) and Conduction Band Minima (CBM) energy levels shows that both oxides act as electron acceptors and inject holes into the diamond structure. Hence, those metal oxides can be described as p-type doping materials for the diamond. Additionally, our work suggests that by depositing appropriate metal oxides in an oxygen rich atmosphere or using metal oxides with high stochiometric ration between oxygen and metal atoms could lead to an increase of the charge transfer between the diamond and oxide, leading to enhanced surface transfer doping. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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10 pages, 1666 KiB  
Article
Nanoscale MOSFET as a Potential Room-Temperature Quantum Current Source
by Kin P. Cheung, Chen Wang and Jason P. Campbell
Micromachines 2020, 11(4), 364; https://doi.org/10.3390/mi11040364 - 31 Mar 2020
Cited by 7 | Viewed by 3156
Abstract
Nanoscale metal-oxide-semiconductor field-effect-transistors (MOSFETs) with only one defect at the interface can potentially become a single electron turnstile linking frequency and electronic charge to realize the elusive quantized current source. Charge pumping is often described as a process that ‘pumps’ one charge per [...] Read more.
Nanoscale metal-oxide-semiconductor field-effect-transistors (MOSFETs) with only one defect at the interface can potentially become a single electron turnstile linking frequency and electronic charge to realize the elusive quantized current source. Charge pumping is often described as a process that ‘pumps’ one charge per driving period per defect. The precision needed to utilize this charge pumping mechanism as a quantized current source requires a rigorous demonstration of the basic charge pumping mechanism. Here we present experimental results on a single-defect MOSFET that shows that the one charge pumped per cycle mechanism is valid. This validity is also discussed through a variety of physical arguments that enrich the current understanding of charge pumping. The known sources of errors as well as potential sources of error are also discussed. The precision of such a process is sufficient to encourage further exploration of charge pumping based on quantum current sources. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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25 pages, 425 KiB  
Article
A One-Dimensional Effective Model for Nanotransistors in Landauer–Büttiker Formalism
by Ulrich Wulf
Micromachines 2020, 11(4), 359; https://doi.org/10.3390/mi11040359 - 30 Mar 2020
Cited by 8 | Viewed by 3550
Abstract
In a series of publications, we developed a compact model for nanotransistors in which quantum transport in a variety of industrial nano-FETs was described quantitatively. The compact nanotransistor model allows for the extraction of important device parameters as the effective height of the [...] Read more.
In a series of publications, we developed a compact model for nanotransistors in which quantum transport in a variety of industrial nano-FETs was described quantitatively. The compact nanotransistor model allows for the extraction of important device parameters as the effective height of the source-drain barrier, device heating, and the quality of the coupling between conduction channel and the contacts. Starting from a basic description of quantum transport in a multi-terminal device in Landauer–Büttiker formalism, we give a detailed derivation of all relevant formulas necessary to construct our compact nanotransistor model. Here we make extensive use of the the R-matrix method. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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8 pages, 2137 KiB  
Article
Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM
by Hyeonjeong Kim, Songyi Yoo, In-Man Kang, Seongjae Cho, Wookyung Sun and Hyungsoon Shin
Micromachines 2020, 11(2), 228; https://doi.org/10.3390/mi11020228 - 23 Feb 2020
Cited by 10 | Viewed by 4375
Abstract
Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) [...] Read more.
Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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12 pages, 983 KiB  
Article
A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator
by Yannan Zhang, Ke Han and and Jiawei Li
Micromachines 2020, 11(2), 223; https://doi.org/10.3390/mi11020223 - 21 Feb 2020
Cited by 16 | Viewed by 4261
Abstract
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and [...] Read more.
Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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11 pages, 3617 KiB  
Article
Quantum Enhancement of a S/D Tunneling Model in a 2D MS-EMC Nanodevice Simulator: NEGF Comparison and Impact of Effective Mass Variation
by Cristina Medina-Bailon, Hamilton Carrillo-Nunez, Jaehyun Lee, Carlos Sampedro, Jose Luis Padilla, Luca Donetti, Vihar Georgiev, Francisco Gamiz and Asen Asenov
Micromachines 2020, 11(2), 204; https://doi.org/10.3390/mi11020204 - 16 Feb 2020
Cited by 7 | Viewed by 3570
Abstract
As complementary metal-oxide-semiconductor (CMOS) transistors approach the nanometer scale, it has become mandatory to incorporate suitable quantum formalism into electron transport simulators. In this work, we present the quantum enhancement of a 2D Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator, which includes a novel [...] Read more.
As complementary metal-oxide-semiconductor (CMOS) transistors approach the nanometer scale, it has become mandatory to incorporate suitable quantum formalism into electron transport simulators. In this work, we present the quantum enhancement of a 2D Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator, which includes a novel module for the direct Source-to-Drain tunneling (S/D tunneling), and its verification in the simulation of Double-Gate Silicon-On-Insulator (DGSOI) transistors and FinFETs. Compared to ballistic Non-Equilibrium Green’s Function (NEGF) simulations, our results show accurate I D vs. V G S and subthreshold characteristics for both devices. Besides, we investigate the impact of the effective masses extracted Density Functional Theory (DFT) simulations, showing that they are the key of not only the general thermionic emission behavior of simulated devices, but also the electron probability of experiencing tunneling phenomena. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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11 pages, 1512 KiB  
Article
A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications
by Ke Han, Shanglin Long, Zhongliang Deng, Yannan Zhang and Jiawei Li
Micromachines 2020, 11(2), 164; https://doi.org/10.3390/mi11020164 - 03 Feb 2020
Cited by 12 | Viewed by 3394
Abstract
This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology [...] Read more.
This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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11 pages, 3302 KiB  
Article
Transient Simulation for the Thermal Design Optimization of Pulse Operated AlGaN/GaN HEMTs
by Huaixin Guo, Tangsheng Chen and Shang Shi
Micromachines 2020, 11(1), 76; https://doi.org/10.3390/mi11010076 - 09 Jan 2020
Cited by 9 | Viewed by 3622
Abstract
The thermal management and channel temperature evaluation of GaN power amplifiers are indispensable issues in engineering field. The transient thermal characteristics of pulse operated AlGaN/GaN high electron mobility transistors (HEMT) used in high power amplifiers are systematically investigated by using three-dimensional simulation with [...] Read more.
The thermal management and channel temperature evaluation of GaN power amplifiers are indispensable issues in engineering field. The transient thermal characteristics of pulse operated AlGaN/GaN high electron mobility transistors (HEMT) used in high power amplifiers are systematically investigated by using three-dimensional simulation with the finite element method. To improve the calculation accuracy, the nonlinear thermal conductivities and near-junction region of GaN chip are considered and treated appropriately in our numerical analysis. The periodic transient pulses temperature and temperature distribution are analyzed to estimate thermal response when GaN amplifiers are operating in pulsed mode with kilowatt-level power, and the relationships between channel temperatures and pulse width, gate structures, and power density of GaN device are analyzed. Results indicate that the maximal channel temperature and thermal impedance of device are considerably influenced by pulse width and power density effects, but the changes of gate fingers and gate width have no effect on channel temperature when the total gate width and active area are kept constant. Finally, the transient thermal response of GaN amplifier is measured using IR thermal photogrammetry, and the correctness and validation of the simulation model is verified. The study of transient simulation is demonstrated necessary for optimal designs of pulse-operated AlGaN/GaN HEMTs. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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7 pages, 2797 KiB  
Article
A 45 nm CMOS Avalanche Photodiode with 8.4-GHz Bandwidth
by Wenhao Zhi, Qingxiao Quan, Pingping Yu and Yanfeng Jiang
Micromachines 2020, 11(1), 65; https://doi.org/10.3390/mi11010065 - 07 Jan 2020
Cited by 9 | Viewed by 3545
Abstract
Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company [...] Read more.
Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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15 pages, 2933 KiB  
Article
T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)
by Zeqi Chen, Jianping Hu, Hao Ye and Zhufei Chu
Micromachines 2020, 11(1), 64; https://doi.org/10.3390/mi11010064 - 07 Jan 2020
Cited by 2 | Viewed by 2847
Abstract
In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are [...] Read more.
In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are on either side of the vertical channel. The T-shaped channel structure increases the coupling area between the top gate and the front and back gates, which improves the ability of the gate electrodes to control the channel. What’s more, it makes the top gate have almost the same control ability for the channel as the front gate and the back gate. This unique structure design brings a unique function in that the device is turned on only when two or three inputs are activated. Silvaco technology computer-aided design (TCAD) simulations are used to verify the current characteristics of the proposed Ti-TcFET. The current characteristics of the device are theoretically analyzed, and the results show that the theoretical analysis agrees with the TCAD simulation results. The proposed Ti-TcFET devices with three input terminals can be used to simplify the complex circuits in a compact style with reduced counts of transistors compared with the traditional complementary metal–oxide–semiconductor/ fin field-effect transistors (CMOS/FinFETs) with a single input terminal and thus provides a new idea for future circuit designs. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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8 pages, 1447 KiB  
Article
Improved DRUS 4H-SiC MESFET with High Power Added Efficiency
by Hujun Jia, Yuan Liang, Tao Li, Yibo Tong, Shunwei Zhu, Xingyu Wang, Tonghui Zeng and Yintang Yang
Micromachines 2020, 11(1), 35; https://doi.org/10.3390/mi11010035 - 27 Dec 2019
Cited by 5 | Viewed by 2292
Abstract
A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing [...] Read more.
A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE). Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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12 pages, 4888 KiB  
Article
Vertical Field Emission Air-Channel Diodes and Transistors
by Wen-Teng Chang, Hsu-Jung Hsu and Po-Heng Pao
Micromachines 2019, 10(12), 858; https://doi.org/10.3390/mi10120858 - 06 Dec 2019
Cited by 15 | Viewed by 3149
Abstract
Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of [...] Read more.
Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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13 pages, 6377 KiB  
Article
A Smart Floating Gate Transistor with Two Control Gates for Active Noise Control
by Cheng Mao, Cheng Yang, Haowen Ma, Feng Yan and Limin Zhang
Micromachines 2019, 10(11), 722; https://doi.org/10.3390/mi10110722 - 25 Oct 2019
Cited by 3 | Viewed by 3224
Abstract
A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of [...] Read more.
A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of the device was developed to demonstrate the working principle. Theoretical analysis and simulation results proved the superposition of the two control gates. A series of test experiments were carried out and the results showed that the device was in accordance with the basic electrical characteristics of a floating gate transistor, including the current–voltage (I–V) characteristics and the threshold characteristics observed on the two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, which demonstrates the feasibility of the proposed device for active noise control. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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17 pages, 5534 KiB  
Article
Investigation of 1200 V SiC MOSFETs’ Surge Reliability
by Huan Li, Jue Wang, Na Ren, Hongyi Xu and Kuang Sheng
Micromachines 2019, 10(7), 485; https://doi.org/10.3390/mi10070485 - 18 Jul 2019
Cited by 23 | Viewed by 5535
Abstract
In this work, the surge reliability of 1200 V SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) from various manufactures has been investigated in the reverse conduction mode. The surge current tests have been carried out in the channel conduction and non-conduction modes. The experimental results [...] Read more.
In this work, the surge reliability of 1200 V SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) from various manufactures has been investigated in the reverse conduction mode. The surge current tests have been carried out in the channel conduction and non-conduction modes. The experimental results show that the maximum surge currents that the devices can withstand are similar for both cases. It is found that short circuits occurred between the gate and the source in the failed devices. The characteristics of the body diode have also changed after the tests. By measuring the device characteristics after each surge current is applied, it can be concluded that the damages to the gate oxide layer and the body diode occurred only when the maximum surge current is applied. By decapping the failed devices and observing the cross section of the damaged cell, it is found that high temperature caused by excessive current flow through the devices during the surge tests is the main reason for the device failure. Finally, the TCAD simulation of the devices has been carried out to bring insight into the operation of the devices during the surge events. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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7 pages, 1363 KiB  
Article
Improved MRD 4H-SiC MESFET with High Power Added Efficiency
by Shunwei Zhu, Hujun Jia, Xingyu Wang, Yuan Liang, Yibo Tong, Tao Li and Yintang Yang
Micromachines 2019, 10(7), 479; https://doi.org/10.3390/mi10070479 - 17 Jul 2019
Cited by 13 | Viewed by 3253
Abstract
An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based [...] Read more.
An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device is balanced, and the IMRD MESFET with a best power-added efficiency (PAE) is finally obtained. The results show that the PAE of the IMRD MESFET is 68.33%, which is 28.66% higher than the MRD MESFET, and DC and RF performance have not dropped significantly. Compared with the MRD MESFET, the IMRD MESFET has a broader prospect in the field of microwave radio frequency. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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12 pages, 3202 KiB  
Article
Novel High-Energy-Efficiency AlGaN/GaN HEMT with High Gate and Multi-Recessed Buffer
by Shunwei Zhu, Hujun Jia, Tao Li, Yibo Tong, Yuan Liang, Xingyu Wang, Tonghui Zeng and Yintang Yang
Micromachines 2019, 10(7), 444; https://doi.org/10.3390/mi10070444 - 02 Jul 2019
Cited by 9 | Viewed by 5209
Abstract
A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate [...] Read more.
A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdown voltage increases by 16.7%, while the gate-to-source capacitance decreases by 17%. The new structure has a better gain than the conventional HEMT. In radio frequency (RF) simulation, the results show that the HGMRB HEMT has 90.8%, 89.3%, and 84.4% power-added efficiency (PAE) at 600 MHz, 1.2 GHz, and 2.4 GHz, respectively, which ensures a large output power density. Overall, the results show that the HGMRB HEMT is a better prospect for high energy efficiency than the conventional HEMT. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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12 pages, 2417 KiB  
Article
Design of 400 V Miniature DC Solid State Circuit Breaker with SiC MOSFET
by Hui Li, Renze Yu, Yi Zhong, Ran Yao, Xinglin Liao and Xianping Chen
Micromachines 2019, 10(5), 314; https://doi.org/10.3390/mi10050314 - 10 May 2019
Cited by 9 | Viewed by 4106
Abstract
Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have the advantages of high-frequency switching capability and the capability to withstand high temperatures, which are suitable for switching devices in a direct current (DC) solid state circuit breaker (SSCB). To guarantee fast and reliable action [...] Read more.
Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have the advantages of high-frequency switching capability and the capability to withstand high temperatures, which are suitable for switching devices in a direct current (DC) solid state circuit breaker (SSCB). To guarantee fast and reliable action of a 400 V DC SSCB with SiC MOSFET, circuit design and prototype development were carried out. Taking 400V DC microgrid as research background, firstly, the topology of DC SSCB with SiC MOSFET was introduced. Then, the drive circuit of SiC MOSFET, fault detection circuit, energy absorption circuit, and snubber circuit of the SSCB were designed and analyzed. Lastly, a prototype of the DC SSCB with SiC MOSFET was developed, tested, and compared with the SSCB with Silicon (Si) insulated gate bipolar transistor (IGBT). Experimental results show that the designed circuits of SSCB with SiC MOSFET are valid. Also, the developed miniature DC SSCB with the SiC MOSFET exhibits faster reaction to the fault and can reduce short circuit time and fault current in contrast with the SSCB with Si IGBT. Hence, the proposed SSCB can better meet the requirements of DC microgrid protection. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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Review

Jump to: Editorial, Research

21 pages, 2309 KiB  
Review
Reliability of Miniaturized Transistors from the Perspective of Single-Defects
by Michael Waltl
Micromachines 2020, 11(8), 736; https://doi.org/10.3390/mi11080736 - 29 Jul 2020
Cited by 12 | Viewed by 2961
Abstract
To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage [...] Read more.
To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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24 pages, 5732 KiB  
Review
Hybrid Polymer/Metal Oxide Thin Films for High Performance, Flexible Transistors
by Jae Won Jeong, Hye Suk Hwang, Dalsu Choi, Byung Chol Ma, Jaehan Jung and Mincheol Chang
Micromachines 2020, 11(3), 264; https://doi.org/10.3390/mi11030264 - 04 Mar 2020
Cited by 17 | Viewed by 5479
Abstract
Metal oxides (MOs) have garnered significant attention in a variety of research fields, particularly in flexible electronics such as wearable devices, due to their superior electronic properties. Meanwhile, polymers exhibit excellent mechanical properties such as flexibility and durability, besides enabling economic solution-based fabrication. [...] Read more.
Metal oxides (MOs) have garnered significant attention in a variety of research fields, particularly in flexible electronics such as wearable devices, due to their superior electronic properties. Meanwhile, polymers exhibit excellent mechanical properties such as flexibility and durability, besides enabling economic solution-based fabrication. Therefore, MO/polymer nanocomposites are excellent electronic materials for use in flexible electronics owing to the confluence of the merits of their components. In this article, we review recent developments in the synthesis and fabrication techniques for MO/polymer nanocomposite-based flexible transistors. In particular, representative MO/polymer nanocomposites for flexible and transparent channel layers and gate dielectrics are introduced and their electronic properties—such as mobilities and dielectric constant—are presented. Finally, we highlight the advances in interface engineering and its influence on device electronics. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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52 pages, 14703 KiB  
Review
Miniaturization of CMOS
by Henry H. Radamson, Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, Wenjuan Xiong, Junjie Li, Jianfeng Gao, Hong Yang, Shihai Gu, Xuewei Zhao, Yong Du, Jiahan Yu and Guilei Wang
Micromachines 2019, 10(5), 293; https://doi.org/10.3390/mi10050293 - 30 Apr 2019
Cited by 84 | Viewed by 16561
Abstract
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin [...] Read more.
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era. Full article
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
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